Datasheet

AN83
AN83REV2 47
Sheet for additional information on the operation of
the EEPROM.
Driver Configuration Information
The CS8900A supports random access to 16-bit
words in the EEPROM through software control.
Therefore, in addition to the configuration data
stored in the Reset Configuration Block automati-
cally loaded by the CS8900A after each reset, addi-
tional configuration information can be stored in
the EEPROM and accessed by the MAC driver.
Typically, this additional configuration informa-
tion includes the unique IEEE physical address for
the adapter. It may also contain device configura-
tion information used by the MAC driver such as
hardware version, media capabilities, and bus con-
figuration (IRQ, DMA, and memory).
Format of Driver Configuration Block
Table 8 defines the format of the block of configu-
ration information (referred to as the Driver Con-
figuration Block) required for use with MAC
drivers provided by Cirrus. Cirrus recommends all
fields be initialized to their default values before
shipping the adapter. Default values for each field
are indicated in the following sections. All re-
served fields should be set to zero.
Note: The Driver Configuration Block must start at
EEPROM word address 1Ch to ensure compatibil-
ity with MAC drivers supplied by Cirrus.
Addr Word Description
00h A110h Sequential EEPROM, 16 bytes follow
01h 0020h 1 word into PP_020 (IO Base Addr)
02h 0210h IO Base Address = 210h
03h 3030h 4 words beginning at PP_030
04h 8000h Boot PROM base at C8000h
05h 000Ch
06h C000h Boot PROM mask of FC000h (16K)
07h 000Fh
08h 1600h Checksum
Table 7. EEPROM Reset Configuration Block
Addr. Description Bit(s) Function
1Ch IA bits[39-32], bits[47-40] 15-0 IEEE individual node address
1Dh IA bits[ 23-16], bits[31-24] 15-0 IEEE individual node address
1Eh IA bits[ 7-0], bits[15-8] 15-0 IEEE individual node address
1Fh ISA Configuration Flags
Memory Mode Flag 15 0 = memory mode disabled, 1 = memory mode enabled
Boot PROM Flag 14 0 = no Boot PROM, 1= Boot PROM installed
StreamTransfer 13 0 = disabled, 1 = enabled
DMA Burst 12 0 = disabled, 1 = enabled
RxDMA Only 11 0 = disabled, 1 = enabled
Auto RxDMA 10 0 = disabled, 1 = enabled
DMA Buffer Size 9 0 = 16K, 1 = 64K
IOCHRDY Enable 8 0 = disabled, 1 = enabled
Use SA 7 0 = disabled, 1 = enabled
DMA Channel 6-4 0 = DRQ5, 1 = DRQ6, 2 = DRQ7, 3 = DMA Disable
IRQ 3-0 0 = IRQ10, 1 = IRQ11, 2 = IRQ12, 3 = IRQ5
20h PacketPage Mem Base 15-4 12 MSBs of 24-bit address (lower 12 bits assumed = 0)
Reserved 3-0 Reserved for future use, set to 0
21h Boot PROM Base 15-4 12 MSBs of 24-bit address (lower 12 bits assumed = 0)
Reserved 3-0 Reserved for future use, set to 0
22h Boot PROM Mask 15-4 12 MSBs of 24-bit addr mask (lower 12 bits assumed = 0)
Reserved 3-0 Reserved for future use, set to 0
Table 8. EEPROM Driver Configuration Block