CRD5381 Audio A/D Converter w/ Asynchronous Decimation Filter Reference Design Features Analog Performance System Features Advanced Multi-bit Delta-sigma Architecture Output Sample Rate Determined by Input 24-bit Conversion 120 dB Dynamic Range -110 dB THD+N Performance insensitivity to Input Clock Jitter Digital Filter Characteristics 125 dB Stop-band Rejection Phase-Matched Outputs LEFT RIGHT 2 CS5381 A Quad Speed Slave Mode SDOUT SDIN Word, Left/Right, or Fsyn
CRD5381 Description The combination of the CS5381 Analog-to-Digital Converter and CS8421 Asynchronous Sample Rate Converter creates an analog-to-digital conversion system with an asynchronous digital decimation filter that is virtually immune to interface or network jitter. In addition, the CS8421 adds a multi-channel Time Division Multiplexed (TDM) output format option.
CRD5381 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ................................................................................................................ 4 1.1 Sample Clock Domain ....................................................................................................... 4 1.1.1 CS8421 Input Operational Mode .......................................................................... 4 1.1.2 CS5381 Operational Mode ...............................................................................
CRD5381 1. SYSTEM OVERVIEW 1.1 1.1.1 Sample Clock Domain CS8421 Input Operational Mode Serial Audio Interface - Left-Justified. The selection of the serial audio interface format is arbitrary, assuming the serial input format of the CS8421 is in agreement with the serial output format of the CS5381. The selection of the serial audio format is done by connecting a resistor (1.96 kΩ in this application) to either ground or the VL supply. System Clocking - Master mode, LRCK = MCLK/128.
CRD5381 1.2 CS8421 Output and the Interface Clock Domain 1.2.1 CS8421 Output System Clocking The CS8421 serial output is configured as a system clock slave. The advantages are: • Output sample rate is dependent on the frequency of the incoming word clock (OLRCK), set by the user. • Outputs of multiple CS8421 devices are synchronous. • Multiple devices can be configured in a Time Division Multiplexed (TDM) multi-channel interface format.
CRD5381 1.2.5 Latency or Group Delay The system latency, or group delay, is the sum of the CS5381 group delay and the CS8421 group delay. The latency of the CS5381 is 5 samples (5/Fs), and the latency of the CS8421 depends on input and output sample rates, and can be found in the CS8421 data sheet [3]. Table 1 shows the combined group delay for typical output sample rates with a fixed input sampling rate of 195.3125 kHz. . Output Sample Rate Group Delay 48 kHz 1.48 ms 96 kHz .895 ms 192 kHz .
CRD5381 1.3 Filter Response The transition-band response of the CRD5381 is due to the combination of the digital filtering performed by both the CS5381 and the CS8421. Due to the superior stop-band rejection of the CS8421, the combination of the two parts yields a better stop-band rejection then the CS5381 alone.
CRD5381 +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 d B F S -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 40k 41k 42k 43k 44k 45k 46k 47k 48k 49k 50k 51k 52k Hz Figure 2. Transitional Band, 96 kHz Out +0 -5 -10 -15 -20 -25 -30 -35 d B F S -40 -45 -50 -55 -60 -65 -70 -75 -80 40k 50k 60k 70k 80k 90k 100k 110k 120k 130k 140k 150k Hz Figure 3.
CRD5381 2. OPERATION 2.1 Sample Rate Sampling Clock Domain - The Sampling clock domain includes the CS5381 A/D converter and the serial audio input to the CS8421 SRC. The sampling frequency in this clock domain is dictated by the ILRCK frequency of each CS8421, and is derived from the system master clock Y2. The sample rate within this clock domain is fixed at 195.312 kHz. Interface Clock Domain - The Interface clock domain includes the output of the CS8421 SRC.
CRD5381 Table 2 indicates the jumper options for J8 with the associated output data formats and some common clock frequencies. J8 SDOUTA Data Format TDM/SDOUTB Data LRCK INPUT SCLK INPUT Format Frequency Frequency LJ 24-bit Left-Justified 24-bit Left-Justified 48 kHz 3.072 MHz LJ 24-bit Left-Justified 24-bit Left-Justified 96 kHz 6.144 MHz LJ 24-bit Left-Justified 24-bit Left-Justified 192 kHz 12.288 MHz TDM - 4-Channel TDM 48 kHz 6.144 MHz TDM - 4-Channel TDM 96 kHz 12.
CRD5381 J16 Signal Ground RESET OVERFLOW A OVERFLOW B SRC UNLOCK A SRC UNLOCK B Figure 7. Status Indicator and Reset Header, J16 2.6 Analog Inputs The CRD5381 provides four fully differential analog inputs via J9, J11, J7, and J12; shown in Figure 9 and Figure 10. Each analog input has the required analog circuitry to optimize the performance of each CS5381.
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DS563RD1 4. SCHEMATICS 13 CRD5381 Figure 9.
CRD5381 DS563RD1 Figure 10.
DS563RD1 15 CRD5381 Figure 11.
CRD5381 DS563RD1 Figure 12.
DS563RD1 CRD5381 17 Figure 13.
CRD5381 DS563RD1 Figure 14.
CRD5381 5. LAYOUT Figure 15.
CRD5381 Figure 16.
CRD5381 Figure 17.
CRD5381 Figure 18.
CRD5381 Figure 19.
CRD5381 6. REFERENCES [1] AN270- Audio A/D Conversion w/ Asynchronous Decimation Filter web page: http://www.cirrus.com [2] CS5381 - 120 dB, 192 kHz Stereo A/D Converter web page: http://www.cirrus.com/en/products/pro/detail/P1024.html [3] CS8421 - 32-bit, 192 kHz, Asynchronous, Stereo Sample Rate Converter web page: http://www.cirrus.com/en/products/pro/detail/P1082.html 7. REVISION HISTORY Release DB1 Date MAY 2005 Changes 1st Release Table 3.
