CRD5376 Multichannel Seismic Reference Design Features z General Description Four Channel Seismic Acquisition Node – CS3301A geophone amplifiers (2x) – CS3302A hydrophone amplifiers (2x) – CS5372A dual ∆Σ modulators (2x) – CS5376A quad digital filter (1x) – CS4373A ∆Σ test DAC (1x) – Precision voltage reference – Clock recovery PLL z On-board Microcontroller – SPI™ interface to digital filter – USB communication with PC z PC Evaluation Software – Register setup & control – FFT frequency analysis – Tim
CRD5376 REVISION HISTORY Revision Date Changes RD1 FEB 2006 Initial Release. RD2 NOV 2007 BOM change to latest revision of silicon. Minor layout enhancements. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.
CRD5376 TABLE OF CONTENTS 1. INITIAL SETUP ......................................................................................................................... 5 1.1 Kit Contents ....................................................................................................................... 5 1.2 Hardware Setup ................................................................................................................. 5 1.2.1 Default Jumper Settings .........................................
CRD5376 3.4.7 Harmonics ........................................................................................................... 44 3.4.8 Spot Noise ........................................................................................................... 44 3.4.9 Plot Error ............................................................................................................. 44 3.5 Control Panel .....................................................................................................
CRD5376 1. INITIAL SETUP 1.1 Kit Contents The CRD5376 reference design kit includes: • CRD5376 reference design board • USB cable (A to mini-B) • Software download information card The following are required to operate CRD5376, and are not included: • Bipolar power supply with clip lead outputs (± 3.3 V, 300 mA) • PC running Windows XP® or Windows 2000™ with an available USB port • Internet access to download the evaluation software 1.
CRD5376 1.2.1 Default Jumper Settings * indicates the default jumper installation for CRD5376. Amplifier CS3301A CS3302A CH1 U16 *R128 + *R84 R129 CH2 U2 *R86 + *R92 R87 CH3 U33 R95 + R132 *R94 CH4 U3 R58 + R100 *R59 Table 1. Amplifier Pin 13 Jumper Settings CS5376A SDTKI uController MCLK/2 *R74 R83 Table 2. SDTKI Input Jumper Settings Input Clock Jumper 1.024 MHz *R16 2.048 MHz R18 4.096 MHz R82 Table 3.
CRD5376 1.3 1.3.1 Software Setup PC Requirements The PC hardware requirements for the Cirrus Seismic Evaluation system are: • Windows XP®, Windows 2000™, Windows NT™ • Intel® Pentium® 600MHz or higher microprocessor • VGA resolution or higher video card • Minimum 64MB RAM • Minimum 40MB free hard drive space 1.3.
CRD5376 CRD5376 as an unknown USB device. • If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manager go to the properties of the unknown USB API device and select “Update Driver”. • Select “Install from a list or specific location”, then select “Include this location in the search” and then browse to “C:\Program Files\Cirrus Seismic Evaluation\Driver\”. The PC will recognize and install the USBXpress device driver.
CRD5376 1.4 Self-Testing CRD5376 Noise and distortion self-tests can be performed once hardware and software setup is complete. First, initialize the CRD5376 reference design: • Launch the evaluation software and apply power to CRD5376. • Click ‘OK’ on the About panel to get to the Setup panel. • On the Setup panel, select Open Target on the USB Port sub-panel. • When connected, the Board Name and MCU code version will be displayed. 1.4.
CRD5376 • Once the Setup panel is set, select Configure on the Digital Filter sub-panel. • After digital filter configuration is complete, click Capture on the Data Capture sub-panel. • Once the data record is collected, the Analysis panel is automatically displayed. • Select Noise FFT from the Test Select control to display the calculated noise statistics. • Verify the noise performance (S/N) is 124 dB or better. 1.4.
CRD5376 2. HARDWARE DESCRIPTION 2.1 Block Diagram Figure 1.
CRD5376 2.2 Analog Hardware 2.2.1 2.2.1.1 Analog Inputs External Inputs - INA External signals into CRD5376 are from two major classes of sensors, moving coil geophones and piezoelectric hydrophones. Geophones are low-impedance sensors optimized to measure vibrations in land applications. Hydrophones are high-impedance sensors optimized to measure pressure in marine applications. Other sensors for earthquake monitoring and military applications are considered as geophones for this datasheet.
CRD5376 Discrete switching diodes quickly clamp the analog inputs to the power supply rails when the input voltage spikes. These diodes are reverse biased in normal operation and have low reverse bias leakage and capacitance characteristics to maintain high linearity on the analog inputs.
CRD5376 Land Common Mode Filter Specification Common Mode Capacitance Common Mode Resistance Common Mode -3 dB Corner @ 6 dB/octave Value 10 nF + 10% 200 Ω 80 kHz + 10% Land Differential Filter Specification Differential Capacitance Differential Resistance Differential -3 dB Corner @ 6 dB/octave Value 10 nF + 10% 200 Ω + 200 Ω = 400 Ω 40 kHz + 10% Marine Differential Filter Specification Hydrophone Group Capacitance Differential Resistance -3 dB Corner @ 6 dB/octave Value 128 nF + 10% 412 kΩ + 2 kΩ =
CRD5376 Using this level-shifting 3-to-8 demultiplexer scheme allows flexible control of the analog switches without directly coupling them to the digital power supplies. With eight possible decoded outputs from three GPIO pins, multiple combinations of on / off analog switch arrangements are possible. SW[2..
CRD5376 2.2.2 Differential Amplifiers The CS3301A/02A amplifiers act as a low-noise gain stage for internal or external differential analog signals. Analog Signals INA INB OUTR, OUTF GUARD Description Sensor analog input Test DAC analog input Analog rough / fine outputs CS3302A guard output (jumper selection) Digital Signals MUX[0..1] GAIN[0..2] PWDN CLK Description Input mux selection Gain range selection Power down mode enable CS3301A clock input (jumper selection) 2.2.2.1 MCLK/2 Input vs.
CRD5376 2.2.2.2 Rough-Fine Outputs - OUTR, OUTF The analog outputs of the CS3301A/02A differential amplifiers are split into rough charge and fine charge signals for input to the CS5372A ∆Σ modulators. Analog signal traces out of the CS3301A/02A amplifiers and into the CS5372A modulators are 4-wire INR+, INF+, INF-, INR- quad groups, and are routed with INF+ and INF- as a traditional differential pair and INR+ and INR- as guard traces outside the respective INF+ and INF- traces. 2.2.2.
CRD5376 2.2.4 Delta-Sigma Test DAC The CS4373A test DAC creates differential analog signals for system tests. Multiple test modes are available and their use is described in the CS4373A data sheet. Analog Signals OUT BUF CAP VREF Description Precision differential analog output Buffered differential analog output Capacitor connection for internal anti-alias filter Voltage reference analog inputs Digital Signals TDATA MCLK SYNC MODE[0..2] ATT[0..
CRD5376 2.2.5.1 VREF_MOD12, VREF_MOD34, VREF_DAC The voltage reference output is provided to the CS5372A ∆Σ modulators and the CS4373A test DAC through separate low pass RC filters. By separately filtering the voltage reference for each device, signal dependent sampling of VREF by one device is isolated from other devices.
CRD5376 Data is collected through the SD port. SD Port Signals SDTKI SDRDYz SDCLK SDDAT SDTKO Description Token input to initiate an SD port transaction Data ready acknowledge, active low Serial clock input Serial data output Token output (unused on CRD5376) Modulator ∆Σ data is input through the modulator interface. Modulator Signals MCLK MCLK/2 MSYNC MDATA[1..4] MFLAG[1..
CRD5376 The secondary serial port (SPI 2) and boundary scan JTAG port are unused on CRD5376. SPI2 Signals SCK2 SO SI[1..4] Description Serial clock output (unused on CRD5376) Serial data output (unused on CRD5376) Serial data inputs (unused on CRD5376) JTAG Signals TRSTz TMS TCK TDI TDO Description JTAG reset (unused on CRD5376) JTAG test mode select (unused on CRD5376) JTAG test clock input (unused on CRD5376) JTAG test data input (unused on CRD5376) JTAG test data output (unused on CRD5376) 2.3.1.
CRD5376 CRD5376, as an input from the microcontroller to initiate data transactions on command or from the MCLK/2 clock to initiate data transactions automatically as soon as they are available from the digital filter. CS5376A SDTKI uController MCLK/2 R74 R83 Table 7. SDTKI Input Jumper Settings 2.3.2 Microcontroller Included on CRD5376 is an 8051-type microcontroller with integrated hardware SPI and USB interfaces. This C8051F320 microcontroller is a product of Silicon Laboratories (http://www.
CRD5376 C8051F320 has dedicated pins for power and the USB connection, plus 25 general purpose I/O pins that connect to the various internal resources through a programmable crossbar. Hardware connections on CRD5376 limit how the blocks can operate, so the port mapping of microcontroller resources is detailed below. Pin # 1 2 3 4 5 6 7 8 Pin Name P0.1 P0.
CRD5376 Pin # 17 18 19 20 21 22 23 24 Pin Name P2.1 P2.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 Assignment TIMEB SYNC BYP_EN SDA_DE SCL SDA SSIz MOSI Description Time Break signal to CS5376A SYNC signal to CS5376A I2C bypass switch control I2C data driver enable I2C clock in/out I2C data in/out SPI chip select output, active low SPI master out / slave in Pin # 25 26 27 28 29 30 31 32 Pin Name P1.1 P1.0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.
CRD5376 2.3.2.5 Timebreak Signal By default, the C8051F320 microcontroller sends the TIMEB signal to the digital filter for the first collected sample of a data record. By default, 100 initial samples are skipped during data collection to ensure the CS5376A digital filters are fully settled, and the timebreak signal is automatically set for the first ‘real’ collected sample. 2.3.2.
CRD5376 The PLL on CRD5376 uses a voltage controlled crystal oscillator (VCXO) to minimize jitter, and has a single gate phase/frequency detector and clock divider to minimize size and power. 2.3.4 Specification Oscillator - Citizen 32.768 MHz VCXO Surface Mount Package Type Supply Voltage, Current Frequency Stability, Pullability Startup Time Value CSX750VBEL32.768MTR Leadless 6-Pin, 5x7 mm 3.
CRD5376 2.3.4.1 CLK, SYNC Clock and synchronization telemetry signals into CRD5376 are received through RS-485 twisted pairs. These signals are required to be distributed through the external system with minimal jitter and timing skew, and so are normally driven through high-speed bus connections.
CRD5376 version data. Address assignment can be either dynamic or static, depending how the telemetry system is to be implemented. Dynamic address assignment uses daisy-chained I2C connections to assign an address to each measurement node. Once a node receives an address, it enables the I2C bypass switches to the next node so it can be assigned an address. Static address assignment has a serial number assigned to each node during manufacturing.
CRD5376 2.4.1 Analog Voltage Regulators Linear voltage regulators create the positive and negative analog power supply voltages to the analog components on CRD5376. These regulate the +3.3 V and -3.3 V power supply inputs to create the +2.5 V and -2.5 V analog power supplies.
CRD5376 CRD5376 layer 5 is a solid ground plane without splits or routing. A solid ground plane provides the best return path for bypassed noise to leave the system. No separate analog ground is required since analog signals on CRD5376 are differentially routed. CRD5376 layer 6 is dedicated for analog and digital routing. Critical analog signal routes for channels 3 and 4 are on this layer. Some digital routes for the microcontroller are also included on this layer away from the analog signal routes. 2.5.
CRD5376 2.5.3 Bypass Capacitors Each device power supply pin includes 0.1 µF bypass capacitors placed as close as possible to the pin. Each power supply net includes at least 100 µF bulk capacitance as a charge well for transient current loads. VD bypass VA+ bypass CS3301A Device VAbypass Figure 4.
CRD5376 3. SOFTWARE DESCRIPTION 3.1 Menu Bar The menu bar is always present at the top of the software panels and provides typical File and Help pulldown menus. The menu bar also selects the currently displayed panel. Control Description File Load Data Set Loads a data set from disk. Save Data Set Saves the current data set to disk. Copy Panel to Clipboard Copies a bitmap of the current panel to the clipboard. Print Analysis Screen Prints the full Analysis panel, including statistics fields.
CRD5376 3.2 About Panel The About panel displays copyright information for the Cirrus Seismic Evaluation software. Click OK to exit this panel. Select Help Ö About from the menu bar to display this panel.
CRD5376 3.3 Setup Panel The Setup panel initializes the evaluation system to perform data acquisition. It consists of the following sub-panels and controls.
CRD5376 3.3.1 USB Port The USB Port sub-panel sets up the USB communication interface between the PC and the target board. Control Description Open Target Open USB communication to the target board and read the board name and microcontroller firmware version. When communication is established, the name of this control changes to ‘Close Target’ and Setup, Analysis and Control panel access becomes available in the menu bar. Close Target Disconnects the previously established USB connection.
CRD5376 3.3.2 Digital Filter The Digital Filter sub-panel sets up the digital filter configuration options. By default the Digital Filter sub-panel configures the system to use on-chip coefficients and test bit stream data. The on-chip data can be overwritten by loading custom coefficients and test bit stream data from the Customize sub-panel on the Control panel. Any changes made under this sub-panel will not be applied to the target board until the Configure button is pushed.
CRD5376 3.3.3 Analog Front End The Analog Front End sub-panel configures the amplifier, modulator, and test DAC pin options. Pin options are controlled through the GPIO outputs of the digital filter. Any changes made under this sub-panel will not be applied to the target board until the Configure button is pushed. The Configure button writes the new configuration to the target board and then enables the data Capture button.
CRD5376 3.3.5 Gain/Offset The Gain / Offset sub-panel controls the digital filter GAIN and OFFSET registers for each channel. The OFFSET and GAIN registers can be manually written with any 24-bit 2’s complement value from 0x800000 to 0x7FFFFF. The USEGR, USEOR, ORCAL, and EXP[4:0] values enable gain correction, offset correction, and offset calibration in the digital filter. The offset calibration routine built into the digital filter is enabled by writing the ORCAL and EXP[4:0] bits.
CRD5376 3.3.6 Data Capture The Data Capture sub-panel collects samples from the target board and sets analysis parameters. When the Capture button is pressed, the requested number of samples are collected from the target board through the USB port and are split among the enabled channels. A four-channel system, for example, will collect (Total Samples / 4) samples per channel. The maximum number of samples that can be collected is 1,048,576 (1M).
CRD5376 3.3.7 External Macros Macros are generated within the Macros sub-panel on the Control panel. Once a macro has been built it can either be saved with a unique macro name to be run within the Macros sub-panel, or saved as an external macro and be associated with one of the External Macro buttons. A macro is saved as an External Macro by saving it in the . /macros/ subdirectory using the name ‘m1.mac’, ‘m2.mac’, etc.
CRD5376 3.4 Analysis Panel The Analysis panel is used to display the analysis results on collected data. It consists of the following controls.
CRD5376 3.4.1 Test Select The Test Select control sets the type of analysis to be run on the collected data set. Control Description Time Domain Runs a min / max calculation on the collected data set and then plots sample data value vs. sample number. Histogram Runs a histogram calculation on the collected data set and then plots sample occurrence vs. sample value. Only valid for noise data since sine wave data varys over too many codes to plot as a histogram.
CRD5376 3.4.2 Statistics The Statistics control displays calculated statistics for the selected analysis channel. For multichannel data captures, only one channel of calculated statistics are displayed at a time and is selected using the Statistics channel control. Errors that affect statistical calculations will cause the Plot Error control to appear.
CRD5376 3.4.4 Cursor The Cursor control is used to identify a point on the graph using the mouse and then display its plot values. When any point within the plot area of the graph is clicked, the Cursor will snap to the closest plotted point and the plot values for that point display below the graph. When using the Zoom function, the Cursor is used to select the corners of the area to zoom. 3.4.5 Zoom The ZOOM function allows an area on the graph to be expanded.
CRD5376 3.5 Control Panel The Control panel is used to write and read register settings and to send commands to the digital filter. It consists of the following sub-panels and controls.
CRD5376 3.5.1 DF Registers The DF Registers sub-panel writes and reads registers within the digital filter. Digital filter registers control operation of the digital filter and the included hardware peripherals, as described in the digital filter data sheet. Control Description Address Selects a digital filter register. Data Contains the data written to or read from the register. Read Initiates a register read. Write Initiates a register write. 3.5.
CRD5376 3.5.4 Macros The Macros sub-panel is designed to write a large number of registers with a single command. This allows the target evaluation system to be quickly set into a specific state for testing. The Register control gives access to both digital filter registers and SPI1 registers. These registers can be written with data from the Data control, or data can be read and output to a text window.
CRD5376 3.5.6 Customize The Customize sub-panel sends commands to upload custom FIR and IIR filter coefficients, upload custom test bit stream data, start the digital filter, stop the digital filter, and write/read custom EEPROM configuration files to the on-board boot EEPROM. Example data files are included in a sub-directory of the software installation. Control Description Load FIR Coef Write a set of FIR coefficients into the digital filter from a file.
DS612RD2 Rev A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A0 G Cirrus P/N 001-04076-Z1 001-04345-Z1 004-00102-Z1 001-06603-Z1 004-00068-Z1 000-00009-Z1 070-00010-Z1 070-00024-Z1 070-00055-Z1 115-00009-Z1 110-00263-Z1 115-00247-Z1 115-00003-Z1 115-00013-Z1 115-00011-Z1 304-00004-Z1 020-01016-Z1 020-00934-Z1 020-01048-Z1 020-01130-Z1 020-00788-Z1 020-00673-Z1 000-00002-Z1 020-01962-Z1 020-01128-Z1 021-01391-Z1 020-06288-Z1 020-06253-Z1 060-00195-Z1 065-00228-Z2 065-00229
Rev A A A A A A A A A A A0 A D A A A D D1 D A Cirrus P/N 061-00152-Z1 061-00061-Z1 061-00062-Z1 060-00175-Z1 062-00079-Z1 060-00163-Z1 060-00063-Z1 061-00153-Z1 065-00056-Z1 060-00162-Z1 065-00230-Z2 060-00236-Z1 065-00173-Z1 102-00017-Z2 070-00053-Z1 070-00050-Z1 603-00085-Z1 600-00085-Z1 240-00085-Z1 300-00025-Z1 CIRRUS LOGIC CRD5376_REV_D1.
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