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Reference Design and Peripheral Driver Board for CS42L52

Reference Design Board (CRD42L52)

Features

 Ultra-Small Layout

 Stake Header for External System Connections

 1/8” Stereo Input Allows up to 2 Vrms Signals

 1/8” Stereo Headphone Output Jack

 Built-in Switch Control for CS42L52 SPKR/HP

 Stereo Full Bridge Speaker Output Terminal

 Complies with FCC class B and CISPR 22

Standards for Radiated Emissions

Peripheral Driver Board (CDB42LDB1)

Features

 Multiple Power Supply Options

– Three AAA Battery Source

– External Power Supply Header

 S/PDIF I/O (CS8416 Receiver)

– Optical and RCA Input Jacks

 S/PDIF I/O (CS8406 Transmitter)

– Optical and RCA Output Jacks

 FlexGUI S/W Control - Windows

Compatible

– Pre-Defined & User Configurable Scripts

Description

In addition to providing a reference for an ultra small lay-

out design, the purpose of the CRD42L52 is to allow a

quick and easy evaluation of the CS42L52 low power

stereo CODEC.

Two 1/8” stereo jacks on the CRD42L52 provide an in-

terface for analog line-level input and headphone-level

output connections to the CS42L52. Stereo differential

PWM speaker outputs from the CS42L52 can be moni-

tored on a pair of screw terminals on the CRD42L52.

The control port and serial audio interfaces are accessi-

ble via the I/O stake header used to attach the

CRD42L52 to the CDB42LDB1.

The CDB42LDB1 is a peripheral driver board that pro-

vides clock/data, control logic and power supply to the

CRD42L52. Digital data is transmitted and received via

S/PDIF optical and RCA connectors. The CRD42L52

can be programmed by using the Windows Compatible

FlexGUI software provided. Power is derived either

from three AAA batteries or from an external supply on

the CDB42LDB1 driver board and is routed to the

CRD42L52 via the I/O stake header.

ORDERING INFORMATION

CRD42L52 Reference Design

CDB42LDB1 Driver Board

CS42L52

Left

Right

I²C

Control

Port

SAI

Power

Supply

Line

Input

Headphone

Output

Speaker

Microcontroller

S/PDIF Rx

CS8416

S/PDIF Tx

CS8406

12.288 MHz

External

Power

S/PDIF

Input

S/PDIF

Output

USB

I/O Header

AAA Battery

Clip

MCLK

Serial Audio Interface

I²C Control Port

Interface

Micro Reset

Pushbutton

CRD

Placeholder

CRD42L52

CDB42LDB1

APRIL '08

DS680RD1

CRD42L52

Summary of content (28 pages)

PAGE 1
CRD42L52 Reference Design and Peripheral Driver Board for CS42L52 Reference Design Board (CRD42L52) Features Description In addition to providing a reference for an ultra small layout design, the purpose of the CRD42L52 is to allow a quick and easy evaluation of the CS42L52 low power stereo CODEC.
PAGE 2
CRD42L52 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 Power (U2) ....................................................................................................................................... 4 1.2 Microcontroller (U3) ......................................................................................................................... 4 1.
PAGE 3
CRD42L52 LIST OF FIGURES Figure 1.Quick-Start Guide ......................................................................................................................... 6 Figure 2.CRD42L52 and CDB42LDB1 Block Diagram for ADC and DAC Testing ..................................... 7 Figure 3.CRD42L52 and CDB42LDB1 Block Diagram for Digital Loopback Testing .................................. 8 Figure 4.CODEC Configuration Tab .................................................................................
PAGE 4
CRD42L52 1. SYSTEM OVERVIEW The CRD42L52 provides a quick and general overview of the features in the CS42L52 CODEC in addition to providing a reference for an ultra-small layout design. Line, headphone and PWM terminals are accommodated on the board for part evaluation and measurement purposes. The control port and serial audio interfaces are accessible via the I/O stake header used to attach the CRD42L52 to the CDB42LDB1.
PAGE 5
CRD42L52 1.5 Oscillator (Y1) The on-board oscillator provides the system master clock when the digital audio receiver is powered down or when a receiver error occurs in the CS8416. Internal circuitry in the CS8416 automatically sets the oscillator clock as the new system clock whenever a receiver error is detected. This feature allows users to operate the boards without having a S/PDIF input fed to the board at all times. 1.
PAGE 6
CRD42L52 2. QUICK-START GUIDE The following figure is supplied for user convenience as a simplified quick-start guide. Refer to Section 1 on page 4 and Section 3 on page 7 for details on how the various components on the board interface with each other in the different configuration modes. Refer to Section 4 on page 9 for descriptions on control settings in the Cirrus FlexGUI software. 6 Connect Power supply 5 ii between 1.6 V to 5 V. Set switch to desired setting.
PAGE 7
CRD42L52 3. CONFIGURATION OPTIONS This section provides a deeper understanding of on-board circuitry and digital clock and data signal routing for appropriately setting the control software in a specific configuration. The section also provides the expected performance characteristics for the respective configuration mode. CRD42L52 12.
PAGE 8
CRD42L52 Table 2 shows expected performance characteristics when the boards are configured to make analog input to digital output measurements. Plot Location Dynamic Range - Line In to S/PDIF Out Figure 9 on page 15 Frequency Response - Line In to S/PDIF Out Figure 10 on page 15 THD + N - Line In to S/PDIF Out Figure 11 on page 15 Table 2. Line In to S/PDIF Out Performance Plots 3.3 S/PDIF In to Speaker Out Stereo differential speaker outputs from the CS42L52 can be monitored on screw terminals J3 and J4.
PAGE 9
CRD42L52 4. SOFTWARE MODE CONTROL The CRD42L52 may be used with the CDB42LDB1 driver board and the Microsoft® Windows-based FlexGUI graphical user interface, allowing software control of the CS42L52 and FPGA registers. The latest control software may be downloaded from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows: 1. Download and install the FlexGUI software as instructed on the Website. 2.
PAGE 10
CRD42L52 4.1 CODEC Configuration Tab The “CODEC Configuration” tab provides high-level control of various configurations for the CRD42L52. Status text detailing the CODEC’s specific configuration appears directly below the associated control. This text will change depending on the setting of the associated control. A description of each group is outlined below. See the CS42L52 data sheet for complete register descriptions.
PAGE 11
CRD42L52 4.2 Analog Input Volume Tab The “Analog Input Volume” tab provides high-level control of all volume settings in the ADC of the CS42L52. Status text detailing the CODEC’s specific configuration is shown inside the control group of the affected control. This text will change depending on the setting of the associated control. A description of each group is outlined below. See the CS42L52 data sheet for complete register descriptions.
PAGE 12
CRD42L52 4.3 DSP Engine Tab The “DSP Engine” tab provides high-level control of the SDIN (PCM) data volume level, the ADC output/SDIN mix volume level and the overall DAC/PWM channel volume level. DAC/PWM channel Limiter, Tone Control and Beep Generator control functions are also provided. Status text detailing the CODEC’s specific configuration is shown inside the control group of the affected control. This text will change depending on the setting of the associated control.
PAGE 13
CRD42L52 4.4 Analog and PWM Output Volume Tab The “Analog and PWM Output Volume” tab provides high-level control of the CS42L52 input passthrough volume, HP/Line output volume levels, charge pump frequency, speaker volume, and PWM Temperature/Battery monitoring controls. Status text detailing the CODEC’s specific configuration appears directly below the associated control. This text will change depending on the setting of the associated control. A description of each group is outlined below.
PAGE 14
CRD42L52 4.5 Register Maps Tab The Advanced Register Debug tab provides low-level control of the CS42L52 individual register settings. Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push-button for the desired bit. For byte-wise, the desired hex value can be typed directly into the register address box in the register map. The “GPIO” tab may be ignored. Figure 8.
PAGE 15
CRD42L52 5. PERFORMANCE PLOTS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz to 20 kHz (unweighted); VA=VD=VA_HP=1.8 V; Sample Frequency = 48 kHz; HP test load: RL = 10 kΩ. +5 -50 +4.5 -52.5 +4 -55 +3.5 -57.5 +3 -60 +2.5 -62.5 -65 +2 -67.5 +1.5 +1 -70 d B F S -72.5 +0.5 d B F S -75 -77.5 -0 -0.5 -80 -1 -82.5 -1.5 -85 -2 -87.5 -2.5 -90 -3 -92.5 -3.5 -95 -4 -97.5 -4.
PAGE 16
CRD42L52 +0 -60 -62.5 -10 -65 -20 -67.5 -70 -30 -72.5 -40 -75 -77.5 -50 -80 -60 d B r A -70 -80 d B r -82.5 A -87.5 -85 -90 -90 -92.5 -95 -100 -97.5 -110 -100 -102.5 -120 -105 -130 -107.5 -140 20 50 100 200 500 1k 2k 5k 10k -110 20 20k 50 100 200 500 Hz 1k 2k 5k 10k 20k Hz Figure 13. FFT - S/PDIF In to HP Out @ -60 dBFS Figure 14. Dynamic Range - S/PDIF In to HP Out +3 -60 +2.75 -62.5 +2.5 -65 +2.25 -67.5 +2 +1.75 -70 +1.5 -72.5 +1.25 -75 +1 -77.
PAGE 17
CRD42L52 -60 -62 -64 *Note 1 -66 -68 -70 -72 d B r -74 -76 A -78 -80 -82 -84 -86 -88 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 19. THD + N - Line In to HP Out (Dig.
PAGE 18
CRD42L52 6. SYSTEM CONNECTIONS & INTERFACE On CDB42LDB1: Connector/ Interface Reference Designator Input/ Output AAA BT1 BT2 BT3 Input Battery Power Supply. Power Supply Switch S1 Input Switch that selects which power supply is used by the CDB42LDB1 and the CRD42L52. External Power J1 Input +5 V - +2.7 V external power supply. USB J2 Input/Output S/PDIF OPTICAL OUT J7 Output CS8406 digital audio output via optical cable.
PAGE 19
DS680RD1 CRD42L52 AND CDB42LDB1 BLOCK DIAGRAM Speaker CRD42L52 Left USB + J3 Line Input - External Power J4 Microcontroller CS42L52 Right + AAA Battery Clip Headphone Output I²C Control Port SAI Power Supply I²C Control Port Interface Micro Reset Pushbutton CRD Placeholder I/O Header J5 S/PDIF Serial Audio Interface S/PDIF Output Input S/PDIF Rx CS8416 MCLK 12.288 MHz S/PDIF Tx CS8406 CDB42LDB1 Figure 20.
PAGE 20
7. CRD42L52 SCHEMATICS Figure 21.
PAGE 21
DS680RD1 8. CDB42LDB1 SCHEMATICS 21 CRD42L52 Figure 22.
PAGE 22
CRD42L52 DS680RD1 Figure 23.
PAGE 23
CRD42L52 9. CRD42L52 LAYOUT DS680RD1 Figure 24. Silkscreen Top Figure 27. Internal Layer (Ground Plane) Figure 25. Silkscreen Bottom Figure 28. Internal Layer (Power Plane) Figure 26. Top-Side Layer Figure 29.
PAGE 24
CRD42L52 10.CDB42LDB1 LAYOUT Figure 30. Silkscreen Top Figure 31.
PAGE 25
CRD42L52 Figure 32. Top-Side Layer Figure 33.
PAGE 26
CRD42L52 Figure 34. Layer 3 Figure 35.
PAGE 27
CRD42L52 11.
PAGE 28
CRD42L52 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).