Instruction Manual
Table Of Contents
- Features
- Description
- 1. General information
- 2. Schematic Description
- 3. Grounding and Layout
- 4. References
- 4.1 ADDENDUM
- Figure 1. Block Diagram
- Figure 2. CS4202 Audio Codec
- Figure 3. Analog Inputs
- Figure 4. Center Channel, Surround, and Sub-Woofer Outputs
- Figure 5. Front Channel and Headphone Sense Output
- Figure 6. S/PDIF Optical Output
- Figure 7. CNR Connector
- Figure 8. Phase Locked Loop
- Figure 9. Auto Demotion and Serial Buffers
- Figure 10. PCB Layout: Top Assembly Drawing
- Figure 11. PCB Layout: Top Layer
- Figure 12. PCB Layout: Bottom Layer
- Figure 13. PCB Layout: Drill Drawing
- Figure 14. PCB Layout: Top Silkscreen
- 4.1 ADDENDUM
- 5. bill of materials
CRD4202-1
14 DS549RD1A1
R51
NO POP
C68
NO POP
C69
NO POP
R52
NO POP
R53
NO POP
Y2
NO POP
31
2 4
DGND DGND
+3.3VD
DGND
XTAL_OUT
XTAL_IN
ID1#
ID0#
1)
2)
3)
4)
For PLL operation:
OPTIONAL PLL (Phase Locked Loop)
Populate R54 = 1K
DO NOT populate: Y1, C14, C15, and R55
Apply external oscillator to XTAL_IN (pin 2)
(CRD4202-1 can use test oscillator on Y2: ECS-8FA3)
Populate R51, R52, R53, C68, and C69 according to
your input clock rate:
clock rate (MHz) R51 R52 R53 C68 C69
14.31818 2.2K NO POP 0 ohm 0.022uF 220pF
24.576 NO POP NO POP NO POP NO POP NO POP
27 2.2K 0 ohm NO POP 0.022uF 220pF
48 2.2K 0 ohm 0 ohm 0.022uF 220pF
Test Clock Only
Figure 8. Phase Locked Loop