CDB8422 Evaluation Board for CS8422 Features Description IEC-60958, AES3/EBU, S/PDIF Inputs Using the CDB8422 evaluation board is an ideal way to evaluate the CS8422. Use of the board requires a digital signal source, an analyzer, and a power supply. A Windows PC-compatible computer is also required if using software mode to configure the CDB8422.
CDB8422 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 Power ............................................................................................................................................... 4 1.2 Grounding and Power Supply Decoupling ....................................................................................... 4 1.3 FPGA ..........................................
CDB8422 5. JUMPER SETTINGS ........................................................................................................................... 29 6. LEDS .................................................................................................................................................... 29 7. CDB8422 BLOCK DIAGRAM .............................................................................................................. 30 8. CDB8422 SCHEMATICS .....................................
CDB8422 1. SYSTEM OVERVIEW The CDB8422 platform provides S/PDIF and AES3/EBU digital interfaces to the CS8422 and allows for external DSP and I²C® or SPITM control port interconnects. On-board voltage regulators are provided so that a single external power supply of +5 V can be used to provide power for the CDB8422. Optionally, the evaluation board may be powered from a USB connection, which also serves as an interface to a PC.
CDB8422 When the evaluation board is not connected to a PC, the CS8422 is placed in hardware mode and is configured using DIP switches. Certain switch settings require a board reset to take affect, see Section 3.3 for more information. 1.5 CS8406 Digital Audio Transmitter A complete description of the CS8406 transmitter and a discussion of the digital audio interface can be found in the CS8406 data sheet.
CDB8422 2. SOFTWARE MODE Connecting a USB port cable from a PC to the USB connector (J37) on the CDB8422 and launching the provided graphical user interface (Cirrus Logic FlexGUI) software enables one to use the board in software mode. The GUI for the CDB8422 allows the user to configure the CS8422 and FPGA registers via the on-board I²C or SPI control bus. 2.1 Quick Start Guide Figure 1 below is a simplified quick start up guide made for user convenience.
CDB8422 2.2 Configuration Options In software mode, to configure the CDB8422 for making performance measurements, one needs to use Cirrus Logic’s Windows compatible FlexGUI software to program the various components on the board. This section serves to give a deeper understanding of the on-board circuitry and the digital clock and data signal routing involved in several common software mode configurations of the CDB8422.
CDB8422 2.2.2 AES3/EBU In to S/PDIF and PCM Out The CS8422’s AES3/EBU receiver and SRC output performance can be tested by loading the “AES3 In to SPDIF and PCM Out” quick setup file provided with the software package. The script configures the digital clock and data signal routing on the board as shown in Figure 3. Digital AES3/EBU input is provided by the XLR jack J19 to the RXP0 and RXN0 pins of the CS8422.
CDB8422 2.2.3 PCM In to S/PDIF and PCM Out The CS8422’s serial input port and SRC output performance can be tested by loading the “PCM In to SPDIF and PCM Out” quick setup file provided with the software package. The script configures the digital clock and data signal routing on the board as shown in Figure 4. PCM audio input is provided by the PCM input header J22. The jumper position on J23 may be changed to use the MCLK signal from J22 for the CS8422’s XTI signal.
CDB8422 2.2.4 TDM In to TDM Out The CS8422’s TDM output performance can be tested by loading the “TDM In to TDM Out” quick setup file provided with the software package. The script configures the digital clock and data signal routing on the board as shown in Figure 5. TDM audio input data is provided by the TDM input header J30. The LRCK and SCLK signals located at header J30 should be used to clock in the input TDM data.
CDB8422 2.3 Software Mode Control The CDB8422 may be used with the Microsoft® Windows®-based FlexGUI graphical user interface, allowing software control of the CS8422 and FPGA registers. The latest control software may be downloaded from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows: 1. Download and install the FlexGUI software as instructed on the Website. 2.
CDB8422 2.3.1 CS8422 Main Setup Tab The “CS8422 Main Setup” tab provides high-level control of the serial port related registers within the CS8422. A description of each control group is outlined below. See the CS8422 data sheet for complete register descriptions. RMCK Control - Configures the CS8422’s RMCK source and behavior. SAI Control - Configures the serial audio input port of the CS8422. SAO1 and SAO2 Control - Configures the two serial audio output ports of the CS8422.
CDB8422 2.3.2 CS8422 Receiver Controls and Status Tab The “CS8422 Receiver Controls and Status” tab provides high-level control of the CS8422’s S/PDIF receiver register settings. A description of each group is outlined below. See the CS8422 data sheet for complete register descriptions. Receiver Input Control - Configures the CS8422’s receiver input pins and mux. Receiver Data Control - Configures the CS8422’s receiver data processing.
CDB8422 2.3.3 CS8422 Interrupt Controls and Status Tab The “CS8422 Interrupt Controls and Status” tab provides high-level control of the CS8422’s interrupt pin register settings. A description of each control group is outlined below. See the CS8422 data sheet for complete register descriptions. INT Pin Control - Controls the CS8422’s INT pin polarity and modes. Interrupt Error Unmasking - Controls the CS8422’s interrupt error unmasking to affect the INT pin.
CDB8422 2.3.4 FPGA Controls Tab The “FPGA Controls” tab provides high-level control of the on-board FPGA’s register settings. This tab provides controls for MCLK and subclock routing between devices on the CDB8422. Controls for the CS8406 S/PDIF transmitter are also provided. A description of each control group is outlined below. MCLK Routing - Specifies MCLK source for both serial audio output port headers on the board.
CDB8422 2.3.5 Register Maps Tab The Register Maps tabs provide low-level control of the CS8422, FPGA, and GPIO register settings. Register values can be modified bit-wise or byte-wise. “Left-clicking” on a particular register accesses that register and shows its contents at the bottom. The user can change the register contents by using the pushbuttons, by selecting a particular bit and typing in the new bit value, or by selecting the register in the map and typing in a new hex value.
CDB8422 2.4 FPGA Register Quick Reference This table shows the register names and their associated default values.
CDB8422 2.5.2.3 AUX MCLK Source (AUX_Mclk) Default = 0 Function: This bit controls the source of the auxiliary MCLK signal. If the CS8422’s GPO3 pin is selected, the GPO3 pin should be configured to output XTI_OUT (CS8422 register 06h = XFh). AUX_Mclk Setting AUX MCLK Source 0 .......................................... Y4 Canned Oscillator. 1 .......................................... CS8422 pin 30 (GPO3). 2.5.2.
CDB8422 2.5.3.3 SAO2 Subclock Source (SAO2_MS) Default = 00 Function: These bits control the direction of the LRCK and SCLK signals between the SAO2 header J25 and the CS8422. The CS8422’ SAO2 port should be configured in the appropriate master/slave mode. SAO2_MS Setting SAO2 Subclock Source 00 ........................................HDR J25 drives CS8422’s OLRCK2 and OSCLK2 inputs. 01 ........................................CS8422’s OLRCK2 and OSCLK2 outputs drive HDR J25. 10 .........................
CDB8422 2.5.4.3 User Data (UBIT_IN) Default = 0 Function: This bit controls the state of the user data bit for the CS8406’s output S/PDIF data. UBIT_IN Setting User Data Polarity 0 .......................................... Low. 1 .......................................... High. 2.5.4.4 TCBL (TCBL) Default = 0 Function: This bit controls the state of the CS8406’s TCBL pin. TCBL Setting TCBL Polarity 0 .......................................... Low. 1 .......................................... High.
CDB8422 2.5.5 CS8406 Control 2 (Address 05h) 7 Reserved 6 Reserved 2.5.5.1 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 8406_RST 0 AUDIOb CS8406 Reset Pin (8406_RST) Default = 1 Function: This bit controls the state of the CS8406’s RST pin. 8406_RST Setting CS8406 Reset State 0 ..........................................CS8406 in reset. 1 ..........................................CS8406 out of reset. 2.5.5.
CDB8422 3. HARDWARE MODE Powering up the CDB8422 without a USB connection to a PC operates the evaluation board in hardware mode. In this mode, on-board DIP switches allow the user to configure the CDB8422 without the use of a PC and GUI. However, only a subset of configuration options are available in hardware mode. 3.1 Quick Start Guide Figure 11 below is a simplified quick start up guide made for user convenience. The user may choose from steps 7 through 10 depending on the desired measurement.
CDB8422 3.2 Configuration Options In hardware mode, to configure the CDB8422 for making performance measurements, one needs to use the on-board control switches to set up the various components on the board. This section serves to give a deeper understanding of the on-board circuitry and the digital clock and data signal routing involved in two different hardware mode configurations of the CDB8422.
CDB8422 3.2.2 TDM In to TDM Out The CS8422’s TDM output performance can be tested by setting the hardware switches as shown in Table 2. This configures the digital clock and data signal routing on the board as shown in Figure 13. TDM audio input data is provided by the TDM input header J30. The LRCK and SCLK signals located at header J30 should be used to clock in the input TDM data. Optionally, digital AES3/EBU input can be provided by the XLR jack J19 to the RXP0 and RXN0 pins of the CS8422.
CDB8422 3.3 Hardware Mode Control This section provides a full description for the hardware mode control switches S3, S4, and S7, see the tables below. Switches S3 and S4 control the pull-up or pull-down resistor value attached to the MS_SEL and SAOF pins of the CS8422, respectively. Each resistor value is sensed during the power-up sequence to configure the device correctly. Consequently, for a modification to S3 or S4 to take affect, the CDB8422 should be reset by pressing push-button S5.
CDB8422 Switch S4 controls the data format options for both serial output ports, see Table 4 for switch configurations. For SDOUT2, the output resolution will be equal to the resolution of the incoming receiver data. The exception is the case where right-justified mode is selected and the receiver input word-length is an odd number of bits.
CDB8422 Switch S7 controls the remaining options for the CS8422 in hardware mode, see Table 5 for switch configurations. The NV/RERR (CS8422 pin 9) and V/AUDIO (CS8422 pin 10) signals are provided at header J26 pins 5 and 2, respectively, and their states are indicated by LEDs D2 and D3. The TX/U (CS8422 pin 18) signal is provided at pin 1 of J31.
CDB8422 4.
CDB8422 5. JUMPER SETTINGS JMP LABEL PURPOSE POSITION J20 [No Label] Selects voltage source for the CDB8422 1-2 Voltage source is USB connection (J37). *2 - 3 Voltage source is +5 V binding post (J2). J11 J8 J13 J17 DC0 DC1 SHUNTED Bypasses optical S/PDIF input DC coupling capacitor DC2 [No Label] Selects S/PDIF input source to receiver input pins of CS8422 J23 [No Label] Selects XTI clock source for CS8422 J21 J29 0.01 µF series capacitor is shorted. 0.
7. CDB8422 BLOCK DIAGRAM Crystal Oscillator Canned Oscillator Canned Oscillator XTI Jumper Reset RMCK Mux ISCLK OLRCK1 ILRCK SDOUT1 SDIN CS8406 TX Output SDIN OLRCK2 SDOUT2 TDM_IN Header OSCLK2 USB Microcontroller ILRCK CS8422 RX Input USB ISCLK Header Header OSCLK1 Header OMCK I2C/SPI Resistors FPGA Reset CDB8422 DS692DB2 Figure 14.
8. CDB8422 SCHEMATICS CDB8422 DS692DB2 Figure 15.
CDB8422 DS692DB2 Figure 16.
CDB8422 DS692DB2 Figure 17.
CDB8422 DS692DB2 Figure 18.
CDB8422 DS692DB2 Figure 19.
CDB8422 DS692DB2 Figure 20.
CDB8422 DS692DB2 Figure 21.
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CDB8422 DS692DB2 Figure 23.
CDB8422 DS692DB2 Figure 24.
CDB8422 DS692DB2 Figure 25.
CDB8422 DS692DB2 Figure 26.
9. CDB8422 LAYOUT CDB8422 DS692DB2 Figure 27.
CDB8422 DS692DB2 Figure 28.
CDB8422 DS692DB2 Figure 29.
CDB8422 10.REVISION HISTORY Revision Changes DB1 Initial Release DB2 Added S/PDIF receiver sensitivity note to Section 1.8 on page 5. Changed 0.01 pF to 0.01 µF in Table 7 on page 29. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.
