Owner's manual

CDB61884
18 DS485DB1
6. BOARD CONFIGURATIONS
6.1 E1 75 Ω Mode Setup
Table 4 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation
board to operate in E1 75 Ω Hardware, Serial Host and Parallel Host operational modes. Before selecting
Host mode, the switches in Table 4 in bold should be set to the position stated.
3. Connect a standard 25-pin male to female parallel port cable to connector J12 and the control PC.
4. Set “HIGH” to enable BITS Clock Recovery function for only Channel #0 in Hardware Mode.
5. Other settings may be used to enter G.772 Non-Intrusive Monitoring in Hardware Mode. Refer to the
CS61884 Data Sheet for other settings.
6. Set “LOW” to disable receiver Internal line impedance matching function. The external resistors for all
eight receivers must be changed to 9.31 Ω to properly match the input line impedance.
Table 4. E1 75 Ω Operational Mode Switch/Jumper Position
Switches/Jumpers Hardware Serial Host (Note 3) Parallel Host (Note 3)
S15 (MODE) HARDWARE SERIAL HOST PARALLEL HOST
S1 (0) LOOP FUNCTION NONE NONE
S2 (1) LOOP FUNCTION NONE NONE
S3 (2) LOOP FUNCTION NONE NONE
S4 (3) LOOP FUNCTION NONE NONE
S5 (4) LOOP FUNCTION NONE NONE
S6 (5) LOOP FUNCTION NONE NONE
S7 (6) LOOP FUNCTION NONE NONE
S8 (7) LOOP FUNCTION NONE NONE
S9 #1 (MOT_\INTL) HIGH HIGH MOTOROLA/INTEL
S9 #2 (MUX) LOW (Note 4) HIGH MUX/NON-MUX
S9 #3 (A4) LOW (Note 5) HIGH HIGH
S9 #4 (A3) LOW (Note 5) HIGH HIGH
S9 #5 (A2) LOW (Note 5) HIGH HIGH
S9 #6 (A1) LOW (Note 5) HIGH HIGH
S9 #7 (A0) LOW (Note 5) HIGH HIGH
S10 (JASEL) ANY POSITION OPEN OPEN
S11 (CBLSEL) HIGH (Note 6) NC NC
S12 (LEN 2) LOW OPEN OPEN
S13 (LEN 1) LOW OPEN OPEN
S14 (LEN 0) LOW OPEN OPEN
J13(VLOGIC)3V3V3V
J1 (MCLK) OSCILLATOR OSCILLATOR OSCILLATOR
J93 (CLKE) OPEN OPEN OPEN
J23 (TXOE) OPEN OPEN OPEN