Manual

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Cirrus Logic, Inc. 1998

CDB61584A

Product Databook

Dual Line

Interface Unit

FEATURES

■Socketed CS61584A Dual Line Interface

■All Required Components for CS61584A

Evaluation

■Locations to Evaluate Protection Circuitry

■LED Status Indications for Alarm Conditions

■Support for Hardware and Host Modes

DESCRIPTION

The evaluation board includes a socketed CS61584A

dual line interface device and all support components

necessary for evaluation. The board is powered by an

external +5 Volt supply.

The board may be configured for 100Ω twisted-pair T1,

75Ω coax E1, or 120Ω twisted-pair E1 operation. Bind-

ing posts and bantam jacks are provided for line

interface connections. Several BNC connectors provide

clock and data I/O at the system interface. Reference

timing may be derived from a quartz crystal, crystal os-

cillator, or an external reference clock. Four LED

indicators monitor device alarm conditions.

ORDERING INFORMATION:

CDB61584A

Oscillator

Circuit

TTIP1

TRING1

RTIP1

RRING1

TTIP2

TRING2

RTIP2

RRING2

CHANNEL1

CHANNEL2

5V+0V

TCLK1

TPOS1

(TDATA1)

TNEG1

RCLK1

RPOS1

(RDATA1)

RNEG1

(BPV1)

CHANNEL1

RESET

CIRCUIT

V+

TCLK2

TPOS2

(TDATA2)

TNEG2

RCLK2

RPOS2

(RDATA2)

RNEG2

(BPV2)

CHANNEL2

HardwareControl

andModeCircuit

LEDStatus

Indicators

SerialInterface

ControlCircuit

CS61584A

XTL

REFCLK

DS261DB2 MAR ‘98

Summary of content (12 pages)

PAGE 1
CDB61584A Product Databook FEATURES ■ Socketed CS61584A Dual Line Interface Dual Line Interface Unit ■ All Required Components for CS61584A Evaluation ■ Locations to Evaluate Protection Circuitry ■ LED Status Indications for Alarm Conditions DESCRIPTION ■ Support for Hardware and Host Modes The evaluation board includes a socketed CS61584A dual line interface device and all support components necessary for evaluation. The board is powered by an external +5 Volt supply.
PAGE 2
CDB61584A Dual Line Interface Unit POWER SUPPLY - TAOS1, TAOS2: transmit all ones; As shown on the evaluation board schematic in Figures 1-5, power is supplied to the board from an external +5 Volt supply connected to the two binding posts labeled V+ and GND. Zener diode Z1 protects the components on the board from reversed supply connections and over-voltage damage. Capacitor C16 provides power supply decoupling and ferrite bead L1 helps isolate the CS61584A and buffer supplies.
PAGE 3
CDB61584A Dual Line Interface Unit provided when headers J7 and J13 are jumpered in the "AIS" position. The AIS1 and AIS2 LED indicators illuminate when the line interface receiver has detected the all-ones receive input signal. Resistors R26 and R27 pull-down the TNEG(1,2) inputs when coder mode is disabled but headers J7 and J13 are jumpered in the "AIS" position. Further details concerning Host mode operation are described in the "readme.txt" file on the enclosed disk.
PAGE 4
CDB61584A Dual Line Interface Unit REFERENCE CLOCK JTAG ACCESS The CDB61584A requires a T1 or E1 reference clock for operation. This clock may operate at either a 1-X rate (1.544 MHz or 2.048 MHz) or an 8X rate (12.352 MHz or 16.384 MHz) and can be supplied by either a quartz crystal, crystal oscillator, or external reference. The evaluation board is supplied from the factory with two crystal oscillators for T1 and E1 operation. The CS61584A implements JTAG boundary scan to support board-level testing.
PAGE 5
CDB61584A Dual Line Interface Unit EVALUATION HINTS 1) The orientation of pin 1 for the CS61584A is labeled "1" on the left side of the socket U7. 2) A jumper must not be placed on header J10 when using the CDB61584A. 3) Component locations R3-R4, R14-R15, C1, and C12 must have the correct values installed according to the application. All the necessary components are included with the evaluation board.
PAGE 6
CDB61584A Dual Line Interface Unit 3 51.1 17 C26 100pF J2 R30 U2 5 15 U2 51.1 R31 7 U2 51.1 4 6 8 AIS1 U7 CS61584A CHANNEL 1 R38 R39 U2 R6 3 1 2 51.1 3 4 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 51.1 51.1 J-TDO VD+ R26 47K J-TDI C3 .1µF VA+ 2 Q2 R7 R5 J7 1 470 LOS1 D2 LED PD1 ATTEN0 1 470 VD+ TTIP1 J31 T R TRING1 J8A 1 R8 4 R9 J32 J9 1 T1 D10 J33 J8B 6 R24 VD+ 3 5 6 1.
PAGE 7
CDB61584A Dual Line Interface Unit J16 VA+ 11 L2 U3 VCC 1 20 ENA 19 U3 10 GND RCLK2 C32 100pF 13 51.1 J17 R42 7 U3 ENA R41 9 C33 100pF 51.1 5 U3 C34 100pF R43 C15 J18 .1µF 15 RPOS2 (RDATA2) RNEG2 (BPV2) 51.1 J19 U7 CS61584A CHANNEL 2 6 16 4 18 2 U3 C35 100pF N/C-3 60 TCLK2 J20 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 U3 C36 100pF 51.1 51.1 R50 R51 4 3 10K CON32 J-TCK J-TMS VD+ R28 C13 51.1 J13 R27 47K VA+ D6 2 T4 VD+ 1 3 D7 .
PAGE 8
CDB61584A Dual Line Interface Unit VD+ J24 J26 VD+ R56 51.1 26 24 22 20 18 16 14 12 10 8 6 4 2 CS SD1 SCLK R55 3.92k SD0 25 INT 23 21 19 17 15 13 11 9 7 5 3 1 100 pF R40 51.
PAGE 9
CDB61584A Dual Line Interface Unit 29 RV+1 30 RGND1 31 MODE 32 R10 BGREF 4.99k 33 AGND 34 AV+ 35 RESET 36 REFCLK 37 XTALOUT 1XCLK 38 1XCLK 39 RGND2 40 RV+2 U7 CS61584A TIMING CIRCUITRY C5 .1µF C8 Y1 VD+ .1µF C6 .1µF C7 1.0µF VD+ J 10 (must not be jumped) VD+ 1 SW6 R11 SW1 10K 2 R23 47K VD+ VD+ 2 4 VA+ J14 U4 C14 .1µF VCC 1 3 REFCLK 8 GND J15 Figure 4.
PAGE 10
CDB61584A Dual Line Interface Unit GND V+ J23 J22 VA+ C16 47µF Z1 VD+ L1 VD+ Prototyping Area Figure 5.
PAGE 11
• Notes •
PAGE 12
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc.