Manual

ManualsBrandsCirrus Logic ManualsHardwareCDB5528

Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.



Cirrus Logic, Inc. 2000

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

CDB5521/22/23/24/28

CDB5521/22/23/24/28 Evaluation Board and Software

Features

l Evaluation Board and Software Supports All

Chips: CS5521, CS5522, CS5523, CS5524,

and CS5528

l Direct Thermocouple Interface

l RS-232 to PC With Test Modes

l On-board 80C51 Microcontroller

l On-board Voltage Reference

l Lab Windows/CVI

Evaluation Software

– Register Setup & Chip Control

– Data Capture

– FFT Analysis

– Time Domain Analysis

– Noise Histogram Analysis

l On-board Charge Pump Drive Circuitry

General Description

The CDB5521/22/23/24/28 is an inexpensive tool de-

signed to evaluate the performance of the CS5521,

CS5522, CS5523, CS5524, and CS5528 Analog-to-Dig-

ital Converters (ADC).

The evaluation board includes a 2.5 V voltage reference,

an 80C51 microcontroller, an RS232 driver/receiver, and

firmware. The 8051 controls the serial communication

between the evaluation board and the PC via the firm-

ware, thus, enabling quick and easy access to all of the

CS5521/22/23/24/28’s registers.

The CDB5521/22/23/24/28 also includes one installed

ADC sample, and software for Data Capture, Time Do-

main Analysis, Histogram Analysis, and Frequency

Domain Analysis.

ORDERING INFORMATION

CDB5521/22/23/24/28 Evaluation Board

AIN1+

AIN1-

AIN2+

AIN2-

AIN3+

AIN3-

AIN4+

AIN4-

NBV

CPD

NBV DRIVE

CIRCUITRY

CRYSTAL

32.768 kHz

REF+

REF-

VOLTAGE

REFERENCE

+5 ANALOG-5 ANALOG AGND

CS5522

CS5523

CS5524

CS5528

+5 DIGITAL

DGND

LEDs

SCLK

SDO

SDI

80C51

Microcontroller

TEST

SWITCHES

CRYSTAL

11.0592 MHz

RESET

CIRCUITRY

RS232

DRIVER/RECEIVER

RS232

CONNECTOR

on off

CS5521

MAY ‘00

DS317DB2

Summary of content (28 pages)

PAGE 1
\ CDB5521/22/23/24/28 CDB5521/22/23/24/28 Evaluation Board and Software Features General Description l Evaluation The CDB5521/22/23/24/28 is an inexpensive tool designed to evaluate the performance of the CS5521, CS5522, CS5523, CS5524, and CS5528 Analog-to-Digital Converters (ADC).
PAGE 2
CDB5521/22/23/24/28 TABLE OF CONTENTS 1. PART I: HARDWARE ............................................................................................................... 4 1.1 Introduction ........................................................................................................................ 4 1.3 Using the Evaluation Board ............................................................................................... 8 1.4. Power Connections ................................................
PAGE 3
CDB5521/22/23/24/28 Figure 13. CDB5521/22/23/24/28 Component Side (top) ............................................................. 26 Figure 14. CDB5521/22/23/24/28 Solder Side (bottom) ............................................................... 27 LIST OF TABLES Table 1. Header Descriptions.......................................................................................................... 9 Table 2. Microcontroller Read/Write Commands via RS-232 ...............................................
PAGE 4
CDB5521/22/23/24/28 1. PART I: HARDWARE 1.1 Introduction The CDB5521/22/23/24/28 evaluation board provides a means of testing the CS5521/22/23/24/28 Analog-to-Digital Converters (ADCs). The board interfaces the converters to an IBMTM compatible PC via an RS-232 interface while operating from a +5 V and -5 V power supply. To accomplish this, the board comes equipped with an 80C51 microcontroller and a 9-pin RS-232 cable, which physically interfaces the evaluation board to the PC.
PAGE 5
CDB5521/22/23/24/28 R15 10Ω +5V Analog C14 0.1µF C29 10µF 2 1 3 R17 301Ω J1 1 AIN1+ 2 AIN13 AIN2+ 4 AIN2- HDR1 C2 4700pF HDR2 HDR8 C3 4700pF U4 LT1019 +5V Analog C20 0.1µF IN C33 0.1µF HDR9 U6 AIN1CS5521 CS5522* AIN2+ C34 0.1µF 17 R26 301Ω AIN1+ AIN2- 14 C30 10µF CS SDI SDO SCLK A0 A1 DGND Y2 32.768kHz 11 9 8 12 15 6 16 To Figure 3 13 C9 0.033µF CPD 20 OUT R7 C16 20kΩ 0.1µF C15 0.1µF JP7 10 C35 0.1µF R24 49.9Ω GND TRIM XIN XOUT 18 R25 301Ω VD+ AGND C32 0.
PAGE 6
CDB5521/22/23/24/28 R15 10Ω +5V Analog C14 0.1µF C29 10µF 2 1 3 R17 301Ω HDR1 C2 4700pF HDR2 R25 301Ω AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4- 1 2 3 4 5 6 7 8 HDR8 C3 4700pF R26 301Ω HDR9 HDR11 C4 4700pF HDR12 U4 LT1019 C20 0.1µF IN AIN2+/AIN3 AIN2-/AIN4 Y2 32.768kHz 13 11 10 14 17 8 18 To Figure 3 15 C9 0.033µF CPD 9 AIN3-/AIN6 D2 1N4148 C37 0.1µF AIN4+/AIN7 D3 1N4148 C31 4700pF 19 AIN4-/AIN8 HDR14 C39 0.1µF NBV CPD GND 7 337 24 C16 R7 0.
PAGE 7
DS317DB2 A1 A0 SCLK R9 750kΩ Bypass Cap C24 33pF C0G RESET C19 0.1µF +5V Digital 6 5 4 3 2 1 9 19 18 R1 200 Ω R2 200 Ω R3 200 Ω R4 200 Ω R5 200 Ω R6 200 Ω Y1 11.0592MHz C23 33pF C0G CS SDI SDO SCLK A0 A1 C18 0.1µF D4 1N4148 +5V Digital From Figure 1, 2 SDO SDI CS HDR6 RST XTAL2 XTAL1 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 VSS 20 UM1 80C51 39 40 P2.3 P2.2 P2.1 24 23 22 P2.0 21 P3.2 13 P3.3 14 P3.4 12 P3.0 10 11 P3.1 P0.0 VDD +5V Digital R12 5.
PAGE 8
CDB5521/22/23/24/28 1.3 Using the Evaluation Board The CS5521/22/23/24/28 are highly integrated ADCs. They contain a multiplexer, an instrumentation amplifier (IA), a programmable gain amplifier (PGA), an on-chip charge pump drive (CPD), and programmable output word rates (OWR). The IA provides a set gain of 20 while the PGA sets the input levels of the ADC at either 25 mV, 55 mV, 100 mV, 1 V, 2.5 V, or 5 V (for VREF = 2.5 V). The CPD provides a square wave output.
PAGE 9
CDB5521/22/23/24/28 1.6 Software 1.7. Writing Your Own Interface Software The evaluation board comes with software and an RS-232 cable to link the evaluation board to the PC. The executable software was developed with Lab Windows/CVITM and meant to run under WindowsTM 3.1 or later. After installing the software, read the readme.txt file for last minute changes in the software. Additionally, Section 2.
PAGE 10
CDB5521/22/23/24/28 Register Read Command (HEX) Write Command (HEX) Offset Register Physical Channel 1 09 01 Offset Register Physical Channel 2 19 11 Offset Register Physical Channel 3 29 21 Offset Register Physical Channel 4 39 31 Offset Register Physical Channel 5 49 41 Offset Register Physical Channel 6 59 51 Offset Register Physical Channel 7 69 61 Offset Register Physical Channel 8 79 71 Gain Register Physical Channel 1 0A 02 Gain Register Physical Channel 2 1A 12 Gain
PAGE 11
CDB5521/22/23/24/28 Self-Offset Calibration Calibration Command (HEX) Self-Offset Calibration on Setup 1 81 Self-Offset Calibration on Setup 2 89 Self-Offset Calibration on Setup 3 91 Self-Offset Calibration on Setup 4 99 Self-Offset Calibration on Setup 5 A1 Self-Offset Calibration on Setup 6 A9 Self-Offset Calibration on Setup 7 B1 Self-Offset Calibration on Setup 8 B9 Self-Offset Calibration on Setup 9 C1 Self-Offset Calibration on Setup 10 C9 Self-Offset Calibration on Setup 11 D
PAGE 12
CDB5521/22/23/24/28 System-Offset Calibration Calibration Command (HEX) System-Offset Calibration on Setup 1 85 System-Offset Calibration on Setup 2 8D System-Offset Calibration on Setup 3 95 System-Offset Calibration on Setup 4 9D System-Offset Calibration on Setup 5 A5 System-Offset Calibration on Setup 6 AD System-Offset Calibration on Setup 7 B5 System-Offset Calibration on Setup 8 BD System-Offset Calibration on Setup 9 C5 System-Offset Calibration on Setup 10 CD System-Offset Ca
PAGE 13
CDB5521/22/23/24/28 2. PART II: SOFTWARE 2.1 Installation Procedure To install the software: 1) Turn on the PC, running Windows 95TM or later. 2) Insert the Installation Diskette #1 into the PC. 3) Select the Run option from the Start menu. 4) At the prompt, type: A:\SETUP.EXE . 5) The program will begin installation. 6) If it has not already been installed on the PC, the user will be prompted to enter the directory in which to install the CVI Run-Time EngineTM.
PAGE 14
CDB5521/22/23/24/28 2.3 Menu Bars Overview file. The file must comply with the CDBCAPTURE file save format. The format is: part number, throughput (or sample rate), number of conversions, maximum range, and the data conversions. The user is prompted to enter the path and file name of previously saved data. To prevent hardware conflicts, this option is deactivated while in the Setup Window. The menu bar controls the link between windows and allows the user to exit the program.
PAGE 15
CDB5521/22/23/24/28 2.4 Setup Window Overview The Setup Window (Figure 6) allows the user to read and write to the internal register of the converter in either binary or hexadecimal, and acquire real-time conversions. It has quick access control icons that quickly reset the converter, reset the converter’s serial port, or self-calibrate the converter’s offset and gain. The following are controls and indicators associated with this window. • Acquire Data This is a control icon.
PAGE 16
CDB5521/22/23/24/28 • Acquire Data This icon begins a conversion cycle based on the selection of MC, LP, and RC. Depending on the status of these bits, the software will instruct the converter to do single conversions or collect data in the FIFO, and display the information on the screen. Pressing the STOP button will end the conversion cycle. All other icons are disabled during the conversion cycles to avoid hardware conflicts. • Channel • • • Channel Data Boxes 2.
PAGE 17
CDB5521/22/23/24/28 - • Window - Used in the Power Spectrum Window to calculate the FFT. Windowing algorithms include the Blackman, Blackman-Harris, Hand, 5-term Hodie, and 7term Hodie. The 5-term Hodie and 7-term Hodie are windowing algorithms developed at Crystal Semiconductor. If information concerning these algorithms is needed, call technical support. - Average - Sets the number of consecutive FFT’s to perform and average.
PAGE 18
CDB5521/22/23/24/28 • • Config 2.8 Time Domain Window Overview See description in Section 2.6, Histogram Window Overview. The following controls and indicators are associated with the Time Domain Analysis (Figure 10). FREQUENCY • Displays the x-axis value of the cursor on the FFT display. • MAGNITUDE See description in Section 2.6, Histogram Window Overview. • Output • See description in Section 2.6, Histogram Window Overview.
PAGE 19
CDB5521/22/23/24/28 2.9 Calibration Window Overview • The following controls and indicators are associated with the Calibration Menu (Figure 9). • • Gain Hexadecimal Icons Eight input/display icons that allow a user to set/clear the 24 bits in the eight gain registers via 6 hexadecimal nibbles. If the upper nibbles in the registers are zero’s, then leading zero nibbles need to be entered. • This is a control icon. When pressed the offset and gain registers are read.
PAGE 20
CDB5521/22/23/24/28 • • Test Mode 3, Continuously Acquire Single Conversion 2) test the RS-232 link between the PC and the microcontroller. This test mode repetitively acquires a single conversion. To enter this mode, set the test switches to 011 and press reset. A binary three is indicated on the LED’s. By probing HDR6 and using CS as a triggering pin, an oscilloscope or logic analyzer will display in real-time how the microcontroller reads conversion data. HDR7 distinguishes these two subtests.
PAGE 21
CDB5521/22/23/24/28 Figure 5. Main Menu Figure 6.
PAGE 22
CDB5521/22/23/24/28 Figure 7. Data FIFO Window Figure 8.
PAGE 23
CDB5521/22/23/24/28 Figure 9. Calibration Menu Figure 10.
PAGE 24
CDB5521/22/23/24/28 Figure 11.
PAGE 25
CDB5521/22/23/24/28 Figure 12.
PAGE 26
CDB5521/22/23/24/28 Figure 13.
PAGE 27
CDB5521/22/23/24/28 Figure 14.
PAGE 28