Instruction Manual

DS963DB1 25
CDB53L30
6 Schematics
Figure 6-4. Serial Audio Header, Sync I/O
MCLK I N
SCLK
LRCK/FSYNC
1.ASP1_SDOUT
1.ASP2_SDOUT
2.ASP1_SDOUT
2.ASP2_SDOUT
MCLK OUT
Serial Audio Header
Serial Header
To Master Clock
Routing Buffers
C34
0.1uF
X5R
1
VCCA
2
A1
3
A2
4
GND
5
DIR
6
B2
7
B1
8
VCCB
U14
SN74LVC2T45DCUR
R76 0
R77 0
R78 0
R79 0
R80 0
R81 0
C41
0.1uF
X5R
R52 0
1
2
34
56
78
910
11 12
13 14
15 16
J29
R64 0
C42
0.1uF
X5R
1
VCCA
2
A1
3
A2
4
GND
5
DIR
6
B2
7
B1
8
VCCB
U20
SN74LVC2T45DCUR
R75 0
R84 0
C54
0.1uF
X5R
R86 0 R88 0
C55
0.1uF
X5R
1
VCCA
2
A1
3
A2
4
GND
5
DIR
6
B2
7
B1
8
VCCB
U21
SN74LVC2T45DCUR
R90 0
R91 0
C56
0.1uF
X5R
R92 0 R94 0
1
2
3
Q1
NTR4501NT1G
R125
10K
R126
10K
R135 0
R85 0
NO POP
R87 0
NO POP
R63 0
NO POP
R162 0
R164 0
R44
0
NO POP
CS53L30-1.ASP1_SDOUT[2,4]
CS53L30-1.ASP2_SDOUT/AD0[2,4]
CS53L30-2.ASP1_SDOUT[2,4]
CS53L30-2.ASP2_SDOUT/AD0[2,4]
CS53L30-1.SCLK[2]
CS53L30-2.SCLK[2]
CS53L30-1.LRCK/FSYNC[2]
CS53L30-2.LRCK/FSYNC[2]
+1.8V
VA
+1.8V
+1.8V
VA
+1.8V
+1.8V
VA
+1.8V
SERIAL_HDR.M/S
[5]
MCLK_IN[3]
MCLK_OUT[3]
PLL.LRCK_IN[3]
SPDI F_T X.SCLK[4]
SPDI F_T X.LRCK[4]
External
Sync I /O
Header
External Sync I/O
SY NC OUT
SY NC IN
Sync Di rect i on
Jumper
1
VCCA
2
A1
3
A2
4
GND
5
DIR
6
B2
7
B1
8
VCCB
U25
SN74LVC2T45DCUR
C80
0.1uF
X5R
R117 0 R122 0
R115
10K
R116
10K
R119
10K
R120 0
J33
SY NC I/O
R123 0
R93 0
NO POP
R155 0
J37
HDR3X1
+1.8V
VA
CS53L30-1.SYNC[2]
CS53L30-2.SYNC[2]