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Evaluation Board for CS53L21

Features

 Selectable Analog Inputs

– Stereo Line-Level RCA Jacks

– Stereo Microphone 1/8” Jacks

 Stereo Microphone Input Jacks

 8- to 96-kHz S/PDIF Output

– CS8406 Digital Audio Transmitter

 I/O Stake Headers

– External Control Port Accessibility

– External DSP Serial Audio I/O Accessibility

 Independent, Regulated Supplies

 1.8 V to 3.3 V Logic Interface

 Hardware Control

– 4 Pre-Defined Switch Settings

 FlexGUI S/W Control - Windows

Compatible

– Pre-Defined & User-Configurable Scripts

 Layout and Grounding Recommendations

Description

The CDB53L21 evaluation board is an excellent means

for evaluating the CS53L21 ADC. Evaluation requires

an analog audio source, an analog/digital analyzer and

power supplies. Optionally, a Windows

PC-compatible

computer may be used to evaluate the CS53L21 in Soft-

ware Mode.

System timing can be provided by the CS53L21 with

supplied master clock, or by using an I/O stake header

with a DSP connected.

RCA phono jacks are provided for the CS53L21 analog

inputs. 1/8” jacks are also available for microphone in-

puts. A digital data output is available from the CS8406

via RCA phono or optical connectors.

The Windows software provides a GUI to make config-

uration of the CDB53L21 easy. The software

communicates through the PC’s serial port or USB port

to configure the control port registers so that all features

of the CS53L21 can be evaluated. The evaluation board

may also be configured to accept external timing and

data signals for operation in a user application during

system development.

ORDERING INFORMATION

CDB53L21 Evaluation Board

Analog Input

(Line or MIC)

Software Mode

Control Port

CS53L21

S/PDIF Output

(CS8406)

Clocks/Data Header

I²C/SPI Header

FPGA

Oscillator

(socket)

Reset

MCLK

Reset

MCLK

Reset

Hardware Mode

Switches

MARCH '06

DS700DB1

CDB53L21

Summary of content (33 pages)

PAGE 1
CDB53L21 Evaluation Board for CS53L21 Features Description Selectable Analog Inputs The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Evaluation requires an analog audio source, an analog/digital analyzer and power supplies. Optionally, a Windows PC-compatible computer may be used to evaluate the CS53L21 in Software Mode.
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CDB53L21 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 Power ............................................................................................................................................... 4 1.2 Grounding and Power Supply Decoupling ........................................................................................ 4 1.3 FPGA ........................................
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CDB53L21 LIST OF FIGURES Figure 1.General Configuration Tab ............................................................................................................ 8 Figure 2.ADC Configuration Tab ................................................................................................................. 9 Figure 3.ADC Volume Controls Tab .......................................................................................................... 10 Figure 4.Mix Volume Controls Tab ..................
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CDB53L21 1. SYSTEM OVERVIEW The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Digital audio signal outputs are provided, and an FPGA is used for easily configuring the board. Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 13 provide configuration details. The CDB53L21 schematic set has been partitioned into seven pages and is shown in Figures 27 through 33.
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CDB53L21 1.5 CS8406 Digital Audio Transmitter A complete description of the CS8406 transmitter (Figure 29 on page 25) and a discussion of the digital audio interface are included in the CS8406 data sheet. The CS8406 converts the PCM data generated by the CS53L21 to the standard S/PDIF data stream and routes this signal to the optical and RCA connectors.
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CDB53L21 1.9 Stand-Alone Switches The “FPGA H/W Control” and “CS53L21 H/W Control” switches control all Hardware Mode options. Section 3. “Hardware Mode Control” on page 13 provides a description of each topology. 1.10 Control Port Connectors A graphical user interface is available for the CDB53L21, allowing easy manipulation of each register. This GUI interfaces with the CDB via the RS-232 or USB connectors and controls all Software Mode options. Section 2.
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CDB53L21 2. SOFTWARE MODE CONTROL The CDB53L21 may be used with the Microsoft Windows-based FlexGUI graphical user interface, allowing software control of the CS53L21 and FPGA registers. The latest control software may be downloaded from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows: 1. Download and install the FlexGUI software as instructed on the Website. 2. Connect and apply power to the +5.0 V binding post. 3.
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CDB53L21 2.1 General Configuration Tab The “General Configuration” tab provides high-level control of signal routing on the CDB53L21. This tab also includes basic controls for the CS53L21 for quickly setting up the CDB53L21 in simple configurations. Status text detailing the ADC’s specific configuration is shown in parenthesis or appears directly below the associated control. This text may change depending on the setting of the associated control.
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CDB53L21 2.2 ADC Configuration Tab The “ADC Configuration” tab provides high-level control of all setup configurations for the CS53L21. Status text detailing the ADC’s specific configuration is shown in parenthesis or appears directly below the associated control. This text will change depending on the setting of the associated control.
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CDB53L21 2.3 ADC Volume Controls Tab The “ADC Volume Controls” tab provides high-level control of all volume settings in the ADC of the CS53L21. Status text detailing the ADC’s specific configuration is shown in parenthesis or inside the control group of the affected control. This text will change depending on the setting of the associated control.
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CDB53L21 2.4 Mix Volume Controls Tab The “Mix Volume Controls” tab provides high-level control of the ADC channel mix functions. Status text detailing the ADC’s specific configuration is shown in read-only edit boxes or appears directly below the associated control. This text will change, depending on the setting of the associated control.
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CDB53L21 2.5 Register Maps Tab The Advanced Register Debug tab provides low-level control of the CS53L21 individual register settings. Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push-button for the desired bit. For byte-wise, the desired hex value can be typed directly into the register address box in the register map. The “FPGA” and “GPIO” tabs may be ignored. Figure 5.
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CDB53L21 3. HARDWARE MODE CONTROL The CDB may be configured without the use of a software control port through the use of two switches, “FPGA H/W Control” and “CS53L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software Mode. The CDB53L21 automatically enters Hardware Mode upon initial power up, or when exiting Software Mode, by terminating the Cirrus FlexGUI software or by disconnecting the RS-232 serial cable or USB cable. 3.
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CDB53L21 Oscillator CS53L21 MCLK LRCK/SCLK SDOUT CS8406 OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) I/O Header MCLK LRCK/SCLK SDOUT Figure 6. Routing 4 Oscillator CS53L21 MCLK LRCK/SCLK SDOUT CS8406 OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) I/O Header MCLK LRCK/SCLK SDOUT Figure 7.
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CDB53L21 Oscillator CS53L21 MCLK LRCK/SCLK SDOUT CS8406 OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) I/O Header MCLK LRCK/SCLK SDOUT Figure 8. Routing 8 Oscillator CS53L21 MCLK LRCK/SCLK SDOUT CS8406 OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) I/O Header MCLK LRCK/SCLK SDOUT Figure 9.
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CDB53L21 3.2 CS53L21 H/W Control The stand-alone “CS53L21 H/W Control” switch S5 controls the Hardware Mode options of the CS53L21. A description of each switch is outlined in the following table. See the CS53L21 Data Sheet, Section 4.2 “Hardware M ode” for further details on setting these switches. Switch Position M/S (Note 1.) MCLKDIV2 I2S/LJ (Note 2.) LO HI LO HI LO HI Function LRCK and SCLK are inputs to CS53L21. LRCK and SCLK are outputs to CS53L21. Internal MCLK to CS53L21 not divided.
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CDB53L21 4. PERFORMANCE PLOTS +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 d B F S d B F S -80 -90 -100 -80 -90 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 -160 -160 -170 -170 -180 20 -180 20 50 100 200 500 1k 2k 5k 10k 50 100 200 500 20k 1k 2k 5k 10k 20k Hz Hz Figure 10. 0 dB FFT, Single-Speed Mode Figure 11.
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CDB53L21 -80 -66 -68 -82 -70 -84 -72 -74 -86 -76 -78 -88 d B F S -90 -92 -80 -82 -84 -86 -88 -94 -90 -92 -96 -94 -96 -98 -98 -100 20 50 100 200 500 1k 2k 5k 10k -100 20 20k 50 100 200 500 Hz -80 -82 -82 -84 -84 -86 -86 d B F S -90 10k 20k -90 -92 -92 -94 -94 -96 -96 -98 -98 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -100 -120 -10 -100 -80 -60 dBr T T T -40 -20 dBr Figure 18. THD+N vs. Amplitude, Single-Speed Mode Figure 19.
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CDB53L21 +0 +0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 d B F S -1 -1.2 -1 -1.2 -1.4 -1.4 -1.6 -1.6 -1.8 -1.8 -2 20 50 100 200 500 1k 2k 5k 10k -2 20 20k Hz 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 22. Frequency Response, Single-Speed Mode Figure 23. Frequency Response, Double-Speed Mode +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 d B F S -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 50 100 200 500 1k Hz 2k 5k 10k Figure 24.
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CDB53L21 5. SYSTEM CONNECTIONS AND JUMPERS CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENT +5V J26 Input +5.0 V Power Supply. GND J27 Input Ground Reference . RS232 J95 Input/Output Serial connection to PC for SPI / I²C control port signals. USB J94 Input/Output USB connection to PC for SPI / I²C control port signal. S/PDIF OPTICAL OUT OPT2 Output CS8406 digital audio output via optical cable. S/PDIF COAX OUT J68 Output CS8406 digital audio output via coaxial cable.
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CDB53L21 JMP LABEL PURPOSE J31 VL Selects source of voltage for the VL supply J25 VA J28 VD J52 J47 J53 VL VA VD J2 J1 J3 LINEB MUX LINEA MUX (AIN2B Select) POSITION *+1.8V Voltage source is +1.8 V regulator. +2.5V Voltage source is +2.5 V regulator. +3.3V Voltage source is +3.3 V regulator. Selects source of voltage for the VA supply *+1.8V Voltage source is +1.8 V regulator. +2.5V Voltage source is +2.5 V regulator. . Selects source of voltage for the VD supply *+1.
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6. BLOCK DIAGRAM Hardware Mode Switches Software Mode Control Port Figure 27 on page 23 I²C/SPI Header Figure 27 on page 23 Reset Figure 32 on page 28 Reset Hardware Mode Switches Figure 30 on page 26 MCLK S/PDIF Out Analog Input (CS8406) FPGA Figure 29 on page 25 Figure 30 on page 26 CS53L21 Figure 28 on page 24 Figure 27 on page 23 Reset Reset MCLK Oscillator (socket) Figure 31 on page 27 Clocks/Data Header Figure 31 on page 27 CDB53L21 DS700DB1 Figure 26.
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DS700DB1 7. SCHEMATICS CDB53L21 23 Figure 27.
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CDB53L21 DS700DB1 Figure 28.
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DS700DB1 CDB53L21 25 Figure 29.
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CDB53L21 DS700DB1 Figure 30.
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DS700DB1 CDB53L21 27 Figure 31.
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CDB53L21 DS700DB1 Figure 32.
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DS700DB1 CDB53L21 29 Figure 33.
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8. BOARD LAYOUT CDB53L21 CS53L21 CS53L21 CS53L21 CDB53L21 DS700DB1 Figure 34.
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DS700DB1 Figure 35.
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CDB53L21 DS700DB1 Figure 36.
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CDB53L21 9. REVISION HISTORY Revision DB1 Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.