Owner manual

CDB5378
DS639DB4 23
Configuration and data collection are through the SPI port.
Modulator ∆Σ data is input through the modulator interface, and test DAC ∆Σ data is generated by the test
bit stream generator.
Amplifier, modulator and test DAC pin settings are controlled through the GPIO port.
2.3.1.1 Reset Options - BOOT, PLL
Immediately following the reset signal rising edge, the CS5378 digital filter latches the states of the
GPIO[4..6]:PLL[0..2] and GPIO7:BOOT pins. The reset states of the GPIO[4..6]:PLL[0..2] pins select the
master clock input frequency and type, while the reset state of the GPIO7:BOOT pin selects how the
CS5378 digital filter receives configuration data.
At reset the CS5378 digital filter GPIO pins default as inputs with weak pull-up resistors enabled. If left
floating, the GPIO state reads high at reset because of the internal pull-up resistor. A four-position DIP
switch on CDB5378 (S5) can connect 10k Ω pull-down resistors to the GPIO[4..6]:PLL[0..2] or
GPIO7:BOOT pins so they will read low at reset. Because the pin states are latched at reset, GPIO pins
can be programmed and used normally after reset without affecting the PLL and BOOT selections.
Detailed information about the PLL input clock and BOOT mode selections at reset can be found in the
CS5378 data sheet.
SPI1 Signals Description
DRDYz Data ready output, active low
SCK Serial clock
MISO Master in / slave out serial data
MOSI Master out / slave in serial data
SS:EECSz Serial chip select, active low
Modulator Signals Description
MCLK Modulator clock output
MSYNC Modulator synchronization output
MDATA Modulator delta-sigma data inputs
MFLAG Modulator over-range flag inputs
TBSDATA Test DAC delta-sigma data output
GPIO Signals Description
GPIO[0]:MUX[0] Amplifier input mux selection
GPIO[1..3]:MODE[0..2] Test DAC mode selection
GPIO[4..6]:GAIN[0..2] Amplifier gain / test DAC attenuation
GPIO[7]:MUX[1] Amplifier input mux selection