Owner manual

CDB5376
24 DS612DB3
Modulator ∆Σ data is input through the modulator interface.
Test DAC ∆Σ data is generated by the test bit stream generator.
Amplifier, modulator, and test DAC digital pins are controlled by the GPIO port.
The secondary serial port (SPI 2) and boundary scan JTAG port are unused on CDB5376.
Modulator Signals Description
MCLK Modulator clock output
MCLK/2 Modulator clock output, half-speed
MSYNC Modulator synchronization output
MDATA[1..4] Modulator delta-sigma data inputs
MFLAG[1..4] Modulator over-range flag inputs
Test Bit Stream Signals Description
TBSDATA Test DAC delta-sigma data output
TBSCLK Test DAC clock output (unused on CDB5376)
GPIO Signals Description
GPIO[0..1]:MUX[0..1] Amplifier input mux selection
GPIO[2..4]:GAIN[0..2] Amplifier gain / test DAC attenuation
GPIO[5..7]:MODE[0..2] Test DAC mode selection
GPIO[8]:PWDN Amplifier / modulator power down
GPIO[9..10] Available general purpose input/output
GPIO[11]:EECS Chip select for boot EEPROM
SPI2 Signals Description
SCK2 Serial clock output (unused on CDB5376)
SO Serial data output (unused on CDB5376)
SI[1..4] Serial data inputs (unused on CDB5376)
JTAG Signals Description
TRSTz JTAG reset (unused on CDB5376)
TMS JTAG test mode select (unused on CDB5376)
TCK JTAG test clock input (unused on CDB5376)
TDI JTAG test data input (unused on CDB5376)
TDO JTAG test data output (unused on CDB5376)