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Evaluation Board for CS5364

Features

! Single-Ended to Differential Analog Inputs

! 3.3 V Logic Interface

! Connection for DSP Serial I/O

! Windows®-Compatible CDB5364 Software

Supplied by Cirrus to Configure the

CS5364

On-Board CS8406 to Generate S/PDIF and

EIAJ-340 Digital Audio

! Requires Only an Analog Signal Source, Power

Supplies and, optionally, a PC for a Complete

Analog-to-Digital-Converter Evaluation System

Description

The CDB5364 evaluation board is an excellent means

for quickly evaluating the CS5364 24-bit, 192 kHz A/D

converter. Evaluation requires only a digital signal ana-

lyzer, an analog signal source, and a power supply.

On-board DIP switches configure the CS5364 in Stand-

Alone mode, avoiding the need for a PC.

For software-based device configuration, the Control

Port mode is used by attaching a host PC to the Evalu-

ation Board and executing the provided FlexGUI

software.

ORDERING INFORMATION

CDB5364 Evaluation Board

Ain+

Ain-

Clks/Data

Analog

Input

Buffers

RCA

Jacks

8051 Micro

RS232

USB

I²C or SPI

FPGA

Optical

Coaxial

CS8406

AES/EBU

S/PDIF

Transmitter

Buffers

Audio

CS5364 A/D

Clks/Data

Control

S/PDIF

Output

CDB5364

SEPTEMBER '05

DS625DB1

Summary of content (24 pages)

PAGE 1
CDB5364 Evaluation Board for CS5364 Features Description ! Single-Ended to Differential Analog Inputs The CDB5364 evaluation board is an excellent means for quickly evaluating the CS5364 24-bit, 192 kHz A/D converter. Evaluation requires only a digital signal analyzer, an analog signal source, and a power supply. ! 3.3 V Logic Interface ! Connection for DSP Serial I/O On-board DIP switches configure the CS5364 in StandAlone mode, avoiding the need for a PC.
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CDB5364 TABLE OF CONTENTS 1. CDB5364 System Overview..................................................................................................................... 3 2. Quick-Start Guide..................................................................................................................................... 3 3. Detailed Board Features .......................................................................................................................... 3 3.1 Stand-Alone Evaluation ....
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CDB5364 1. CDB5364 SYSTEM OVERVIEW The CDB5364 Evaluation Board provides an excellent means of quickly evaluating the CS5364. A digital audio interface transmitter (CS8406) provides an easy interface to digital audio signal analyzers, including the majority of digital audio test equipment. Standard analog input and digital output connectors are included for quick and reliable board setup. An on-board FPGA is used for configuring the various modes of the CS5364.
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CDB5364 3.1.1 S1 and S4 Switch Operation DIP Switch S1 contains six switches that function as described below. M1,M0 set the device Speed Mode 0x00 Single Speed Master 0x01 Double Speed Master 0x10 Quad Speed Master 0x11 Slave all speed DIF1,DIF0 set the Digital Audio Interface Data format 0x00 Left Justified 0x01 I²S 0x10 TDM 2-wire 0x11 TDM 4-wire TDM1 and TDM0 support both TDM mode and PCM mode.
PAGE 5
CDB5364 3.2 Control-Port Evaluation The CDB5364 is shipped with a Cirrus Logic designed Microsoft Windows-based program that allows full control over the CS5364 internal registers. This software program is called the FlexGUI, and it is loaded by executing the FlexLoader.exe file. Hardware interface to the FlexGUI is provided by connecting an RS-232 cable or a USB cable between a host PC and the CDB5364.
PAGE 6
CDB5364 3.3 FlexGUI Hi-Level View The Cirrus Logic FlexGUI defaults to the Hi-Level View as shown in Figure 1. This view provides functionally grouped control over the CS5364, reducing the need to memorize the exact location of bit settings. Any register may be modified at any time; however, the effect of changes made to the CS5364 is gated off until the Control Port Bit is enabled.
PAGE 7
CDB5364 3.4 FlexGUI Low-Level View The Low-level Register Map view provides direct control over the CS5364, the FPGA and GPIO settings that change the CS5364 device address. Select the desired device tab; then select and modify any writeregister values. Register modification is always a READ-WRITE-READ operation and is usable at both the byte or bit level. For byte-level control, type the required hex value in the desired register field numerical box.
PAGE 8
CDB5364 3.5 3.5.1 Bit Definitions CS5364 Bits The Low-Level view of the FlexGUI provides the full register set of the CS5364 under the CS5364 tab. The CS5364 datasheet provides full details of internal register operation. 3.5.2 FPGA Bits FPGA Register 0x00 is non-functional and only contains the revision code of the FPGA. FPGA Register 0x01 is a functional register that provides the following functionality. Figure 3. FPGA Low-Level Bit View Fs_Range1,0 set the device Speed Mode.
PAGE 9
CDB5364 In TDM mode, SDOUT_SEL1 and SDOUT_SEL 0 extract two stereo pairs from the CS5364 TDM stream, convert the data to Left-Justified PCM format and send the data to the CS8406 data input pin. 0x00 TDM Pair 1 (Channel 1, 2) 0x01 TDM Pair 2 (Channel 3, 4) 0x1x Reserved In PCM mode, SDOUT_SEL1 and SDOUT_SEL 0 select which SDOUT pin of the CS5364 is sent to the CS8406. 0x00 SDOUT1 (Channel 1, 2) 0x01 SDOUT2 (Channel 3, 4) 0x1x Reserved TDM2PCM/PCM selects the clock source for the CS8406.
PAGE 10
CDB5364 4.2 Switches The CDB5364 Evaluation Board switches are used for setting speed modes and format protocols and for resetting devices to their default state. The switch functions are described in Table 2. .
PAGE 11
CDB5364 4.5 Power Supply Circuitry Power is applied to the evaluation board through five binding posts (+5 V, +12 V, -12 V, VA and GND). The GND connection is the common reference for power supplies. The +5 V binding post supplies digital power for all logic devices. The +12 V and -12 V binding posts supply power for the Operational Amplifier input buffers. The VA binding posts supplies power to the Analog Reference. 4.
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5. SCHEMATICS CDB5364 DS625DB1 Figure 4.
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DS625DB1 Figure 5.
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CDB5364 DS625DB1 Figure 6.
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DS625DB1 15 CDB5364 Figure 7.
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Figure 8.
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Figure 9.
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DS625DB1 Figure 10.
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Figure 11.
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DS625DB1 Figure 12.
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6. BOARD LAYOUT AND ROUTING PLOTS CDB5364 DS625DB1 Figure 13.
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CDB5364 DS625DB1 Figure 14.
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DS625DB1 23 CDB5364 Figure 15.
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CDB5364 7. REVISION HISTORY Release DB1 Date September 2005 Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.