Manual

CDB5345
DS658DB1 11
5. FPGA REGISTER DESCRIPTION
5.1 CODE REVISION ID - ADDRESS 01H
Function:
Identifies the revision of the FPGA code. This register is Read-Only.
5.2 MCLK SOURCE CONTROL - ADDRESS 02H
5.2.1 MCLK SOURCE (BIT 0)
Default = 0
Function:
This bit selects the source of the CS5345 MCLK signal. Table 1 shows the available settings.
76543210
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0
76543210
Reserved Reserved Reserved Reserved Reserved Reserved Reserved MCLK
Table 1. MCLK Source
MCLK MCLK Source
0 Canned Oscillator
1 M1 position on PCM1 I/O Header