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DS886DB11

CDB47xxx

Evaluation Kit

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CDB47xxx

User’s Manual

Summary of content (87 pages)

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CDB47xxx Evaluation Kit CDB47xxx User ’s Manual Copyright 2014 Cirrus Logic, Inc. http://www.cirrus.
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CDB47xxx User’s Manual Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
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CDB47xxx User’s Manual Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-iii Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-v Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-vii Chapter 1.
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CDB47xxx User’s Manual 1.5.4 Clock and Data Flow for DAI Input with Matched DAO Fs ...........................................1-17 1.6 Other Useful Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17 1.6.1 Web Sites .....................................................................................................................1-17 1.6.2 DSP Information ..................................................................................
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CDB47xxx User’s Manual 5.1.3.1 Creating a Flash Image .................................................................................5-5 5.1.3.2 Programming the Flash Image into the Flash Device ....................................5-5 Chapter 6. CDB47xxx Schematics ....................................................................... 6-1 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 6.
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CDB47xxx User’s Manual Figure 1-6. CDB47xxx-DC28 Daughtercard Block Diagram ......................................................................1-11 Figure 1-7. CDB47xxx-DC24 Daughtercard Block Diagram ......................................................................1-12 Figure 1-8. ADC Clocking ...........................................................................................................................1-14 Figure 1-9. S/PDIF Clocking ...................................................
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CDB47xxx User’s Manual Figure 6-13. CDB47xxD (Differential) Board Block Diagram ......................................................................6-17 Figure 6-14. CDB47xxD (Differential) Board Schematic Index ..................................................................6-18 Figure 6-15. CDB47xxD (Differential) Daughtercard Connectors ..............................................................6-18 Figure 6-16. CDB47xxD (Differential) Digital Audio Control Connectors ............................
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CDB47xxx Kit Contents CDB47xxx User’s Manual Chapter 1 Kit Contents and Requirements 1.1 CDB47xxx Kit Contents Each CDB47xxx kit comes with the items listed in Table 1-1. Table 1-1. CDB47xxx Kit Contents CRD Kit Item Quantity CDB47xxxS-DC48 CDB47xxxS-DC28 CDB47xxxS-DC24 CDB47xxxS Single-Ended Development Board with integrated MCU & USB interface with daughtercard populated with either the CS47048, CS4028, or CS47024 DSP.
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CDB47xxx Kit Contents CDB47xxx User’s Manual Figure 1-1. CDB47xxxS-DCxx Kit Contents Figure 1-2.
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Requirements CDB47xxx User’s Manual 1.2 Requirements 1.2.1 PC Requirements • Microsoft® Windows® XP with Service Pack 2 or higher or Windows 7 (32– or 64–bit) Operating System • USB 2.0 Support 1.2.2 Software Requirements • Cirrus® Evaluation Software Package (available from your local Cirrus Logic representative) 1.2.
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CDB47xxx Main Board System Description CDB47xxx User’s Manual 1.3 CDB47xxx Main Board System Description A detailed block diagram of the CDB47xxxS Development Board is shown in Figure 1-3. The block diagram of the CDB47xxxD Development Board is shown in Figure 1-4 The sections that follow provide a detailed description of each block. Figure 1-3.
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CDB47xxx Main Board System Description CDB47xxx User’s Manual I2S HDRs SPDIF - IN COAX Header will be available to probe / bring in I2S signals SPDIF - IN OPTICAL I2S IN HDR 20 Pin HDR Standard 20 Pin Debug Header (Serial Control & Debug) Mic Pre-Amp Circuitry Digital Buffer DSP Daughtercard The Chronos DSP Daughercard will have only the DSP. Diff Amp This allows us to easily swap out the DSP for different CS47xxx Family members.
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CDB47xxx Main Board System Description CDB47xxx User’s Manual 1.3.1.3 Optical Digital Input (J21) Optical digital inputs have the following characteristics: • Connector Type: Fiber Optic RX for Digital Audio, JIS F05 (TOSLINK) 1.3.1.4 Coaxial Digital Input (J4) Coaxial digital inputs have the following characteristics: • Connector Type: RCA Female • Input Impedance: 75 • Maximum Signal Level: 1.
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CDB47xxx Main Board System Description CDB47xxx User’s Manual 1.3.2.3 Coaxial Digital Output (J35) The coaxial digital output has the following characteristics: • Connector Type: RCA Female • Maximum Signal Output Level: 1Vp-p into 75 load 1.3.2.4 DSP Digital Audio Output (DAO) (J24 or DAO) The DAO connector has the following characteristics: • Connector Type: 2x10, 0.100 inch Male Header • Absolute Maximum Signal Level: +3.6V • Absolute Minimum Signal Level: -0.3V 1.3.
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CDB47xxx Main Board System Description CDB47xxx User’s Manual selection header. Pin 1 of each header is marked with a triangle and the word “REG”. Pin 2 of each header is labeled with the voltage required for that pin (+5V, +3.3V, or +1.8V). 1.3.
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CDB47xxx Main Board System Description CDB47xxx User’s Manual 1.3.9 C8051 MCU The C8051 (U15) is a USB slave controller and general purpose MCU used to control the CDB47xxx Board in stand-alone applications, and also used to interface to the PC through the USB port (DSP Composer). Standalone applications can be as simple as using the MCU to configure the inputs on the board to feed the DSP and provide a power-on-reset (POR) to the DSP.
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CDB47xxx Daughtercard System Description CDB47xxx User’s Manual 1.4 CDB47xxx Daughtercard System Description The CS470xx Audio SOC Daughtercard is exactly the same for both the CDB47xxxS and CDB47xxxD evaluation kits. All of the analog and digital audio signals are fed to the CS470xx (U1) through the daughtercard connectors (J2 - J3). All of the analog pins of the CS470xx are connected to the analog daughtercard connector (J3).
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CDB47xxx Daughtercard System Description CDB47xxx User’s Manual Figure 1-6. CDB47xxx-DC28 Daughtercard Block Diagram 1-11 Copyright 2014 Cirrus Logic, Inc.
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CDB47xxx Daughtercard System Description CDB47xxx User’s Manual Figure 1-7. CDB47xxx-DC24 Daughtercard Block Diagram 1.4.1 Audio Inputs 1.4.1.1 Analog Line-level Inputs (J3) Analog line-level inputs have the following characteristics: • Connector Type: High-Density High-Speed Shrouded Female Connector • Absolute Maximum Signal Level: These signals should only be driven from the connectors on the main board. Voltages should comply with the Max Signal Level specification for the main board circuitry. 1.
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CDB47xxx Daughtercard System Description CDB47xxx User’s Manual 1.4.2 Audio Outputs from the CS470xx DSP 1.4.2.1 Analog Line-level Outputs (J3) Analog line-level outputs have the following characteristics: • Connector Type: High-Density High-Speed Shrouded Female Connector • Maximum Signal Output Level: These signals should only be driven from the connectors on the main board. Voltages will comply with the Max Signal Level specification for the main board circuitry. 1.4.2.
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Audio Clocking CDB47xxx User’s Manual 1.5 Audio Clocking Clocking architecture is one of the most important aspects of an audio system. This can also be one of the most complicated parts of a system design to insure that clocking is valid and stable for all scenarios. This is one of the major advantages of the CS470xx Audio System On-a-Chip (ASOC). Because of the integrated ADC and DAC along with the integrated SRCs, the CS470xx makes audio clocking very simple.
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Audio Clocking CDB47xxx User’s Manual 1.5.2 Clock and Data Flow for S/PDIF Input Figure 1-9. S/PDIF Clocking The S/PDIF clocking architecture is used when any S/PDIF RX is used as an audio source, whether from the optical RX, coaxial RX, or brought in on the DAI header. Figure 1-9 illustrates this clocking configuration. The incoming S/PDIF stream is always rate matched to another MCLK in the system through an SRC.
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Audio Clocking CDB47xxx User’s Manual 1.5.3 Clock and Data Flow for DAI Input with Fixed Output Fs Figure 1-10. DAI Clocking with Variable Input Fs and Fixed Output Fs The DAI clocking architecture is used when any serial audio data source is connected to the DAI header. Figure 1-10 illustrates this clocking configuration. Note that the incoming DAI data is passed out of the CS470xx at the Fs of the crystal connected to the ASOC.
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Other Useful Information CDB47xxx User’s Manual 1.5.4 Clock and Data Flow for DAI Input with Matched DAO Fs Figure 1-11. DAI Clocking with Fixed Output Fs The DAI clocking architecture is used when any serial audio data source is connected to the DAI header. Figure 1-11 illustrates this clocking configuration. Note that the incoming DAI data is synchronized to the DAO using a common MCLK.
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Other Useful Information CDB47xxx User’s Manual 1.6.3 Board Information • The following information can be obtained from your local Cirrus Logic representative. • Schematics • BOM • Artwork and PCB stackup 1.6.4 DSP Software Utility Information The following information can be obtained from your local Cirrus representative.
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Introducing the CDB47xxx Customer Development Kit CDB47xxx User’s Manual Chapter 2 Introduction to CDB47xxx Kit 2.1 Introducing the CDB47xxx Customer Development Kit The CDB47xxx kit is composed of the CDB47xxxS or CDB47xxxD main board and a daughtercard that can support any member of the CS470xx Audio SOC (ASOC) family. The CDB47xxx provides a practical platform for emulating a typical multi-channel audio system application.
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Identifying CDB47xxx Components CDB47xxx User’s Manual • Fast boot – master boot of custom applications from 32 Mbit serial SPI Flash device or 512 kbit I2C device. • Microphone input with integrated amplifier. • Supports all members of the CS470xx family in the 100-pin LQFP package. Note: Not all features of the CS470xx are exercised on the CDB47xxx. 2.2 Identifying CDB47xxx Components 2.2.1 CDB47xxxS Board Figure 2-2 shows the top side of the CDB47xxxS Board. Section 2.2.1.
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DS886DB11 . 24 23 10 21 20 Copyright 2014 Cirrus Logic, Inc 22 18 Identifying CDB47xxx Components CDB47xxx User’s Manual 2-3 Figure 2-2.
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Identifying CDB47xxx Components CDB47xxx User’s Manual 2.2.1.1 CDB47xxxS Board (Single-Ended) Components The circled numbers found in Figure 2-2 refer to the CDB47xxxS board (single-ended) components in the following list. 1. +9V Power In 2. Optical S/PDIF Out 3. Coax S/PDIF Out 4. Optical S/PDIF In 5. Coax S/PDIF In 6. +5V Header 7. Line-Level Analog Outputs 8. CDB47xxS-DC48 Daughtercard Connectors 9. Mic Input 10. Single-Ended Line-Level Inputs 11. MCU Rotary Encoder 12. MCU Buttons 13. SPI Flash 14.
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DS886DB11 . 10 23 21 20 Copyright 2014 Cirrus Logic, Inc 22 18 Identifying CDB47xxx Components CDB47xxx User’s Manual 2-5 Figure 2-3.
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Identifying CDB47xxx Components CDB47xxx User’s Manual 2.2.2.1 CDB47xxxD Board (Differential) Components The circled numbers found in Figure 2-3 refer to the CDB47xxxD board (differential) components in the following list. 1. +9V Power In 2. Optical S/PDIF Out 3. Coax S/PDIF Out 4. Optical S/PDIF In 5. Coax S/PDIF In 6. +5V Header 7. Line-Level Analog Outputs 8. CDB47xxD-DC48 Daughtercard Connectors 9. Mic Input 10. Differential Line-Level Inputs 11. MCU Rotary Encoder 12. MCU Buttons 13. SPI Flash 14.
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Identifying CDB47xxx Components CDB47xxx User’s Manual 10 8 11 9 7 6 5 4 3 2 1 Figure 2-4. CDB47xxx-DC48 Daughtercard 2.2.3.1 CDB47xxx-DC48 Daughtercard Components The circled numbers found in Figure 2-4 refer to the CDB47xxx-DC48 daughtercard components in the following list. 1. Cirrus Logic CS47048 DSP 2. Power LEDs (2) 3. MCLK-XTAL_OUT Header 4. DSP GPIO Button 5. DSP GPIO LED 6. DSP GPIO LED 7. DSP GPIO Switch 8. +1.8VD Probe Point 9. +3.3VD Probe Point 10. +1.8VA Probe Point 11. +3.
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Installation, Setup, and Running First Application CDB47xxx User’s Manual Chapter 3 Installation and Setup of Development Board Software 3.1 Installation, Setup, and Running First Application It is important to install the CDB47xxx Board software before connecting the USB cable from the PC to the USB port of the CDB47xxx Board. Failure to install the evaluation software before the initial connection can result in an inability to communicate with the CDB47xxx. 3.1.
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Installation, Setup, and Running First Application CDB47xxx User’s Manual 5. Make Audio Input connections to the CDB47xxx Board. • Connect one end of the digital audio S/PDIF optical cable to (J1) on the CDB47xxx Board. • Connect the other end of the optical cable to the optical output on the back of a DVD player or other digital audio source. 6.
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Installation, Setup, and Running First Application CDB47xxx User’s Manual which is launched after the CDB47xxx Evaluation Kit is installed and thereafter when the user’s system is rebooted, displays the Device name as “CS47xxx_board”. Look for the CDM icon in the Windows System Icon Tray (located, by default, in the lower-right side of the task bar). Caution: The Cirrus Device Manager must be running in order for the board to operate correctly. 3.1.
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Introduction CDB47xxx User’s Manual Chapter 4 Programming the CDB47xxx Board 4.1 Introduction With the exception of the power selection jumpers, the CDB47xxx is configured exclusively through software. The DSP Composer™ software is a graphical user interface (GUI) that is used to program the CS470xx DSP, and to configure the CDB47xxx. This chapter provides basic instructions for using the GUI to control the CDB47xxx.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual Figure 4-1. ADC In / DAC Out Example 4.2.1 System Block All designs must contain the System block. In DSP Composer, when you drag the System block onto the workspace, the dialog box shown in Figure 4-2 is displayed. This dialog box provides options for selecting the Target chip associated with the development board, the Firmware version (memory map), Core Speed, Reference Clock Frequency (Ref. clock freq.), and the Autodetect Fs.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual Chip ID specifies the minimum Cirrus DSP chip that must be connected to the PC. The choices are CS47024, CS47028, and CS47048 Software designed for a lower numbered chip runs on a higher numbered chip. Table 4-1. Chip ID and Audio Terminals Chip ID Audio Input Terminals Audio Output Terminals CS47024 2 (AIN_1a, b not supported) 4 (AOUT_5–AOUT_8 not supported) CS47028 2 (AIN_1a, b not supported) 8 CS47048 4 8 4.2.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual 4.2.2.1 Audio In via ADC To deliver analog audio data to the DSP via the CS470xx ADCs, drag the Audio In block to the workspace and select an input configuration that includes ADC. The ADC2 input includes a 5:1 input multiplexer that is controlled by the pull-down list, ADC2 Ch 3+4 Input Sel, shown in Figure 4-4. Figure 4-4. ADC2 Device Properties.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual shown in Figure 4-5. Figure 4-5. Selecting ADC2 input Terminals using Device Properties Dialog 4.2.2.3 I2S Audio Input To deliver data to the DSP via I2S, drag the Audio In block to the canvas and choose an input combination that includes I2S as shown in Figure 4-6. As stated in the dialog box, you must connect an I2S Signal before pressing “GO!” Figure 4-6. Selecting Multi-Channel I2S Input 4-5 Copyright 2014 Cirrus Logic, Inc.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual 4.2.3 Input Channel Remap All designs, regardless of the input sources chosen, must include the Input Remap block which maps the input sources to the internal channels of the DSP. Drag the Input Remap block to the workspace, rightclick on the Remap Audio Input block, and choose Device Properties. Figure 4-7 shows the channel map/ remap options that are available. Figure 4-7.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual 4.2.5 Selecting the Audio Output Configuration Configure the audio outputs to the DSP by dragging and dropping the Audio Out block onto the workspace. The dialog box shown in Figure 4-8 appears. Choose from one of the supported output combinations as described in the subsections, Section 4.2.5.1 to Section 4.2.5.3. DAC is selected by default.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual Note that the Device Properties dialog box allows the user to select analog (DAC) outputs only, digital outputs only, or a mixture of the two. If digital outputs are enabled, then the two drop down lists at the bottom of the dialog box allow for DAO2 and DAO3 to be configured to output data in either I2S or S/PDIF format. 4.2.5.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual Figure 4-9. Selecting S/PDIF Outputs and I2S Outputs using Device Properties Dialog 4-9 Copyright 2014 Cirrus Logic, Inc.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual 4.2.5.3 I2S Audio Input Output To output audio data from the DSP via I2S, drag the Audio In block to the canvas and choose an input combination that includes I2S as shown in Figure 4-10. Draw wires from the Output Remap block to the Audio Out block for the desired mappings. Figure 4-10. Selecting I2S Outputs using Device Properties Dialog 4.2.
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Running the ADC In / DAC Out Example Application CDB47xxx User’s Manual Figure 4-11. CDB47xxx Communication Modes / Flash Type 4-11 Copyright 2014 Cirrus Logic, Inc.
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Programming a Serial Flash Device for Master or Slave Boot Operations CDB47xxx User’s Manual Chapter 5 Using DSP Composer or Micro-Condenser Application to Create and Load a Flash Image 5.1 Programming a Serial Flash Device for Master or Slave Boot Operations The CDB47xxx is populated with a 32-Mbit SPI (U17), a 512-kbit I2C (U16), and a 32-Mbit SPI (U14) Flash devices. The SPI Flash (U17), and I2C Flash (U16), devices can be used to store custom DSP firmware or run-time firmware configuration files.
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Programming a Serial Flash Device for Master or Slave Boot Operations CDB47xxx User’s Manual Figure 5-1. Project Properties Dialog Showing the Selection of the I2C Protocol for Loading the Flash Image 3. Click the Advanced button and choose one the supported Flash types that will be receiving the Flash image download. When downloading a Flash image to a customer board, customers should consult their schematics to determine the Flash type to select.
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Programming a Serial Flash Device for Master or Slave Boot Operations CDB47xxx User’s Manual Figure 5-2. Selecting Flash Type via the Advanced Properties Dialog Box 5-3 Copyright 2014 Cirrus Logic, Inc.
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Programming a Serial Flash Device for Master or Slave Boot Operations CDB47xxx User’s Manual The two JP1 checkboxes allow the user to do one of the following: • JP1 Pin 12--Check this box to three-state JP1 Pin 12 signal (mute) which leaves the audio outputs unmuted on the CDB47xxx. This actions allows the user to install an external mute control such as a DSP GPO. • JP1 Pin 16-- Check this box to three state JP1 Pin 16 signal (flash_hold) which releases the DSP SPI Flash (U17).
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Programming a Serial Flash Device for Master or Slave Boot Operations CDB47xxx User’s Manual 5.1.3 Using Micro-Condenser to Create and Load a Flash Image into the DSP 5.1.3.1 Creating a Flash Image To use the Micro-Condenser application to create and load a Flash image to the CS470xx DSP on the CDB47xxx Board, follow these steps: Follow these steps to create the Flash image: 1. Complete examples are included with the evaluation kits: C:\CirrusDSP\micro_condenser\CS47XXX\example 2.
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Introduction CDB47xxx User’s Manual Chapter 6 CDB47xxx Schematics 6.1 Introduction The schematics included in this document are the original Revision A schematics of the CDB47xxx and reflects the board as it was manufactured. Newer schematics may be available that incorporate feature additions or corrections, and may not match Rev. A hardware. 6.2 CDB47xxS Single-Ended Schematic Descriptions 6.2.1 CDB47xxxS Block Diagram Figure 6-1 shows the CDB47xxxS block diagram. 6.2.
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CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual The audio output connectors consist of the following: • 1 RCA jack for coaxial S/PDIF output • 1 optical jack for S/PDIF output • 1 2x10 header for serial audio data (I2S) There is one control connector - JP1.
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CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual populated. The current limiter is scaled to make the CDB47xxxS capable of accepting analog signals of up to 2 VRMS. The CS470xx analog inputs register full-scale for an input amplitude of 2VRMS with this input filter. 6.2.8 Output Filters Figure 6-9 shows the output filters for the CDB47xxxS.
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DS886DB11 SPDIF - IN COAX I2S HDRs SPDIF - IN OPTICAL Header will be available to probe / bring in I2S signals CDB47XXXS I2S IN HDR 20 Pin HDR Standard 20 Pin Debug Header (Serial Control & Debug) Buffer Mic Pre-Amp Circuitry Digital DSP Daughtercard Mic Input Jack The Chronos DSP Daughercard will have only the DSP. This allows us to easily swap out the DSP for different CS47xxx Family members. Analog Digital DAO Buttons/LEDs RCA IN 2 ch (x4) RCA IN 2ch DAO pins on Chronos are also GPIO.
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CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Figure 6-2. CDB47xxS (Sngle-ended) Board Schematic Index 6-5 Copyright 2014 Cirrus Logic, Inc.
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DS886DB11 6-6 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-3.
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DS886DB11 6-7 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-4.
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DS886DB11 6-8 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-5.
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DS886DB11 6-9 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-6.
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DS886DB11 6-10 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-7.
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DS886DB11 6-11 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-8.
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DS886DB11 6-12 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-9.
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DS886DB11 6-13 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-10.
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DS886DB11 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc 6-14 Figure 6-11.
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DS886DB11 6-15 CDB47xxS Single-Ended Schematic Descriptions CDB47xxx User’s Manual Copyright 2014 Cirrus Logic, Inc Figure 6-12.
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CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6.3 CDB47xxD Differential Schematic Descriptions 6.3.1 CDB47xxxD Block Diagram Figure 6-13 shows the CDB47xxxD block diagram 6.3.2 Daughtercard Connectors Figure 6-15 shows the schematic for the daughtercard connectors on the CDB47xxxD board. See section Section 6.2.2 for description of circuitry. 6.3.
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CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6.3.9 MCU Block Diagram Figure 6-22 shows the MCU block diagram for the CDB47xxxD. 6.3.10 MCU Figure 6-23 shows the MCU for the CDB47xxxD. See section Section 6.2.10 for description of circuitry. 6.3.11 User Interface Devices Figure 6-12 shows the buttons, LEDs, and InfraRed receiver which comprise the standalone user interface for the CDB47xxxD. See section Section 6.2.11 for description of circuitry.
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DS886DB11 CDB47XXXD_REV_A. s c h- 1 - Thu J an 29 18: 21: 59 2009 CDB47XXXD I2S HDRs SPDIF - IN COAX Header will be available to probe / bring in I2S signals SPDIF - IN OPTICAL I2S IN HDR 20 Pin HDR Standard 20 Pin Debug Header (Serial Control & Debug) Mic Pre-Amp Circuitry Digital Buffer DSP Daughtercard The Chronos DSP Daughercard will have only the DSP. Diff Amp DAO Buttons/LEDs Stereo 1/8" IN 2 ch (x4) Analog Digital DAO pins on Chronos are also GPIO.
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CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual Figure 6-14. CDB47xxD (Differential) Board Schematic Index 6-19 Copyright 2014 Cirrus Logic, Inc.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-20 Figure 6-15.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-21 Figure 6-16.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-22 Figure 6-17.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-23 Figure 6-18.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-24 Figure 6-19.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-25 Figure 6-20.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-26 Figure 6-21.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-27 Figure 6-22.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-28 Figure 6-23.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxD Differential Schematic Descriptions CDB47xxx User’s Manual 6-29 Figure 6-24.
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CDB47xxx-DC48 Daughtercard Schematic CDB47xxx User’s Manual 6.4 CDB47xxx-DC48 Daughtercard Schematic 6.4.1 CDB47xxx-DC48 Block Diagram Figure 6-25 shows the CDB47xxx-DC48 block diagram 6.4.2 CDB47xxx-DC48 Schematic The schematic for the CDB47xxx-DC48 daughtercard is shown in Figure 6-26. The CDB47xxx-DC48 employs the CS47048 DSP. The DSP is driven by an external crystal circuit. This fixed 24.
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DS886DB11 CDB47XXX_DC48 Analog Connector DC_ID SHIFT REG DAC OUTPUTS GPIO Copyright 2014 Cirrus Logic, Inc I2S In I2S Out Analog Connector Serial Control S/PDIF In S/PDIF Out ADC CS47xxx LED x 2 INPUTS SWITCH BUTTON Current Measure Point +3.3VD Current Measure Point Current Measure Point +1.8VD +3.3VA Current Measure Point +1.8VA POWER CONNECTOR 6-31 Figure 6-25.
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DS886DB11 Copyright 2014 Cirrus Logic, Inc CDB47xxx-DC48 Daughtercard Schematic CDB47xxx User’s Manual 6-32 Figure 6-26.
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Obtaining Schematic Updates CDB47xxx User’s Manual 6.5 Obtaining Schematic Updates Updates to the schematics for the CDB47xxx Development Board can be can be obtained from your local Cirrus Logic representative as part of a design package including the associated BOM, and layout artwork. The schematics are provided in Adobe’s portable document format (PDF) and PADS™ format.
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Troubleshooting Guide CDB47xxx User’s Manual Chapter 7 Troubleshooting 7.1 Troubleshooting Guide This section provides solutions to problems that users might experience when using the CDB47xxx. 7.1.1 Power LEDs Problem: Power LEDs are not illuminated. • Possible cause: DC power supply is not connected to CDB47xxx. Solution: Ensure the DC wall supply is connected to the DC power input jack (J22), and the supply is plugged into a wall outlet.
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Troubleshooting Guide CDB47xxx User’s Manual 7.1.3 Audio is not Heard Problem: Audio cannot be heard. Possible cause: Wrong S/PDIF Source is selected. Solution: Check to make sure that the LED next to the desired S/PDIF source is ON. If not, use MCU to select the appropriate S/PDIF input.
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Revision History CDB47xxx User’s Manual Revision History Revision Date DB7 March, 2012 7-3 DB8 August, 2012 DB9 November, 2012 Changes Added Windows 7 to PC requirements of Section 1.2.1. Updated schematics screenshots in Chapter 6. Added note to Section 3.1.3 regarding USB connectivity issues. Added board image to cover page. DB10 October, 2013 Updated Figure 4-8, Figure 4-9, and Figure 4-10. DB11 February, 2014 Updated Figure 4-2, Figure 4-3, and Figure 4-7.