User Manual

DS792DB1 17
CDB43L22
5. SYSTEM CONNECTIONS AND JUMPERS
CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENT
VP J35 Input +2.7 V to +5.25 V Power Supply.
GND J4 Input Ground Reference.
USB J94 Input/Output USB connection to PC for I²C control port signals.
S/PDIF OPTICAL IN OPT3 Input CS8416 digital audio input via optical cable.
S/PDIF COAX IN J61 Input CS8416 digital audio input via coaxial cable.
I/O Header J8 Input/Output I/O for Clocks & Data directly to/from the CS43L22.
S/W CONTROL J109 Input/Output I/O for external I²C control port signals.
MICRO JTAG J110 Input/Output I/O for programming the micro controller (U84).
FPGA JTAG J75 Input/Output I/O for programming the FPGA (U5).
MICRO RESET S4 Input Reset for the micro controller (U84).
FPGA PROGRAM S2 Input Reload Xilinx program into the FPGA from Flash (U14).
H/W BOARD RESET S1 Input Reset for the CS43L22(U1).
AIN1
AIN2
J33
J37
Input
Input
1/8” audio jacks for analog passthrough input signal to CS43L22.
AIN3
AIN4
J45
J50
Input
Input
1/8” audio jacks for Line or MIC analog passthrough input signals to
CS43L22.
A(RC LPF)
B(RC LPF)
J6
J18
Output
Output
30 kHz LPF version of the signal on speaker binding posts (Used for mea-
surement purposes only).
SPEAKER A-
SPEAKER A+
SPEAKER B-
SPEAKER B+
J60
J59
J101
J99
Output
Output
Output
Output
Full Bridge speaker outputs.
HP/Line Output J40 Output Stereo 1/8” jack for line outputs. When headphones are plugged in to HP
Connect (on J21), this output may be used for performance measure-
ment.
HP Connect J21 Output Stereo headphone jack for Headphone outputs.
I/O HDR J78 Input/Output I/O for clocks and input for DAC SDIN. Signals are passed through the
FPGA for muxing with the S/PDIF input.
Table 4. System Connections