User Manual

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Evaluation Board for CS43L22

Features

 Analog Passthrough Input

– Four Stereo Line Input Jacks

– Channel Mixer

 Analog Output

– Stereo Headphone Jack w/ HP Detect

Capability

– Speaker Output via Differential Stereo

PWM Terminals and Audio Jacks

 8- to 96-kHz S/PDIF Interface

– Optical and RCA S/PDIF Input Jacks

– CS8416 Digital Audio Receiver

 I/O Stake Headers

– External Control Port Accessibility

– External DSP Serial Audio I/O Accessibility

 Multiple Power Supply options via Battery or

External Power Supplies.

 1.8 V to 3.3 V Logic Interface

 FlexGUI S/W Control - Windows

Compatible

– Pre-Defined & User-Configurable Scripts

Description

Using the CDB43L22 evaluation board is an ideal way

to evaluate the CS43L22. Use of the board requires an

analog/digital signal source, an analyzer and power

supplies. A Windows

PC-compatible computer is also

required in order to configure the CDB43L22.

System timing can be provided by the CS8416, by the

CS43L22 with supplied master clock, or via an I/O stake

header with a DSP connected. 1/8th inch audio jacks

are provided for the analog passthrough inputs and

HP/Line outputs. Two pairs of banana jacks and an ad-

ditional pair of 1/8th inch audio jacks are provided to

monitor the stereo differential speaker PWM output

from the CS43L22. Digital input connections are via

RCA phono or optical connectors to the CS8416

(S/PDIF Rx).

The Windows-based software GUI provided makes

configuring the CDB43L22 easy. The software commu-

nicates through the PC’s USB port to configure the

board and FPGA registers so that all features of the

CS43L22 can be evaluated. The evaluation board may

also be configured to accept external timing and data

signals for operation in a user application during system

development.

ORDERING INFORMATION

CDB43L22 Evaluation Board

USB

µ controller

CS43L22

S/PDIF Input

(CS8416)

PSIA Input

Header

FPGA

Oscillator

(socket)

C Interface

Reset

PLL

Clk/Data

SRC

(CS8421)

Analog Output

(Line + Headphone)

Speaker

Outputs

Analog

Passthrough

Input

External System

Input Header

OCTOBER '07

DS792DB1

CDB43L22

Summary of content (31 pages)

PAGE 1
CDB43L22 Evaluation Board for CS43L22 Features Description Analog Passthrough Input Using the CDB43L22 evaluation board is an ideal way to evaluate the CS43L22. Use of the board requires an analog/digital signal source, an analyzer and power supplies. A Windows PC-compatible computer is also required in order to configure the CDB43L22.
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CDB43L22 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 Power ............................................................................................................................................... 4 1.2 Grounding and Power Supply Decoupling ....................................................................................... 4 1.3 FPGA .........................................
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CDB43L22 Figure 21.THD+N vs. HP Output Power ................................................................................................... 29 Figure 22.Freq. Resp. - S/PDIF Input to HP Output .................................................................................. 29 Figure 23.THD+N - S/PDIF Input to HP Output ........................................................................................ 29 Figure 24.Dynamic Range- S/PDIF Input to HP Output .........................................
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CDB43L22 1. SYSTEM OVERVIEW The CDB43L22 platform provides analog and digital interfaces to the CS43L22 and allows for external DSP and I²C® interconnects. On-board power regulators are provided so that an external power supply upto +5 V can be used to provide power for the digital and analog cores of the CS43L22. On-board peripherals are powered from the USB connection which also serves as an interface to a PC.
PAGE 5
CDB43L22 The CS43L22 is configured using the Cirrus FlexGUI. The device configuration registers are accessible via the “Register Maps” tab of the Cirrus FlexGUI software. This tab provides low-level control of each bit. For easier configuration, additional tabs provide high-level control. Section 4 “Software Mode Control” on page 11 provides configuration details. 1.
PAGE 6
CDB43L22 necting headphones to either output jack, the on-board resistive load should be disconnected by removing the jumpers on each stake header(J3 and J9). The CDB43L22 also has A/B speaker output banana jacks (2 per A or B channel) and 1/8“ jack outputs (1 per A or B channel). Stake headers J15 and J19 allow one to short the differential outputs of Channel A and B together, in order to monitor MONO PWM output from the CS43L22.
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CDB43L22 2. QUICK START GUIDE The following figure is a simplified quick start up guide made for user convenience. The following start up guide configures the board with a 1.8 V power supply to VL, VA, VA_HP and VD. The user may choose from steps 9 through 13 depending on the desired measurement. Refer to Section 3 on page 8 for details on how the various components on the board interface with each other in different board configuration modes.
PAGE 8
CDB43L22 3. CONFIGURATION OPTIONS In order to configure the CDB43L22 for making performance measurements, one needs to use Cirrus Logic’s Windows compatible FlexGUI software to program the various components on the board. This section serves to give a deeper understanding of the on-board circuitry and the digital clock and data signal routing involved in the different configuration modes of the CDB43L22.
PAGE 9
CDB43L22 3.2 SPDIF In to Stereo Speaker Out The CS43L22’s stereo differential PWM speaker output performance can be tested by loading the “SPDIF In to Stereo Speaker Out” quick setup file provided with the software package. The script configures the digital clock and data signal routing on the board as shown in Figure 2. Stereo output jacks J6 and J18 can be used to monitor filtered PWM output for measurement purposes.
PAGE 10
CDB43L22 3.3 SPDIF In to Mono Speaker Out The CS43L22’s mono differential PWM speaker output performance can be tested by loading the “SPDIF In to Mono Speaker Out” quick setup file provided with the software package. The script configures the digital clock and data signal routing on the board as shown in Figure 2. Stereo output jacks J6 and J18 can be used to monitor filtered PWM output for measurement purposes.
PAGE 11
CDB43L22 4. SOFTWARE MODE CONTROL The CDB43L22 may be used with the Microsoft Windows®-based FlexGUI graphical user interface, allowing software control of the CS43L22, FPGA and CS8416 registers. The latest control software may be downloaded from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows: 1. Download and install the FlexGUI software as instructed on the Website. 2. Connect and apply power to the +5.0 VP binding post. 3.
PAGE 12
CDB43L22 4.1 Board Configuration Tab The “Board Configuration” tab provides high-level control of signal routing on the CDB43L22. This tab also includes basic controls that allow “quick setup” in a number of simple board configurations. Status text detailing the CS43L22’s specific configuration appears directly below the associated control. This text may change depending on the setting of the associated control.
PAGE 13
CDB43L22 4.2 Passthrough, Power and Serial Audio Interface Configuration Tab The “Passthrough, Power and Serial Audio Interface Configuration” Tab provides high-level control of the CS43L22 passthrough, power control and serial port register settings. Status text detailing the CS43L22’s specific configuration is shown in parenthesis or appears directly below the associated control. This text will change depending on the setting of the associated control. A description of each group is outlined below.
PAGE 14
CDB43L22 4.3 DSP Engine Tab The “DSP Engine” tab provides high-level control of the SDIN (PCM) data volume level, the PCM mix volume level and the overall DAC/PWM channel volume level. DAC/PWM channel Limiter, Tone Control and Beep Generator control functions are also provided. Status text detailing the CS43L22’s specific configuration is shown in parenthesis or inside the control group of the affected control. This text will change depending on the setting of the associated control.
PAGE 15
CDB43L22 4.4 Analog and PWM Output Volume Tab The “Analog and PWM Output Volume” tab provides high-level control of the CS43L22 PWM outputs, HP/Line output volume levels and charge pump frequency. This tab also provides controls for the PWM output including speaker volume and PWM gain. Temperature and Battery monitoring controls for the PWM/Speaker outputs are also on this tab.
PAGE 16
CDB43L22 4.5 Register Maps Tab The Register Maps tabs provide low-level control of the CS43L22, CS8416, CS8421, FPGA and GPIO register settings. Register values can be modified bit-wise or byte-wise. “Left-clicking” on a particular register accesses that register and shows its contents at the bottom. The user can change the register contents by using the push-buttons, by selecting a particular bit and typing in the new bit value or by selecting the register in the map and typing in a new hex value.
PAGE 17
CDB43L22 5. SYSTEM CONNECTIONS AND JUMPERS CONNECTOR REF INPUT/OUTPUT VP J35 Input SIGNAL PRESENT +2.7 V to +5.25 V Power Supply. GND J4 Input USB J94 Input/Output Ground Reference. S/PDIF OPTICAL IN OPT3 Input CS8416 digital audio input via optical cable. S/PDIF COAX IN J61 Input CS8416 digital audio input via coaxial cable. USB connection to PC for I²C control port signals. I/O Header J8 Input/Output I/O for Clocks & Data directly to/from the CS43L22.
PAGE 18
CDB43L22 6. JUMPER SETTINGS JMP LABEL PURPOSE POSITION FUNCTION SELECTED *+1.8V Voltage source is +1.8 V regulator. +2.5V Voltage source is +2.5 V regulator. +3.3V Voltage source is +3.3 V regulator. VL Selects source of voltage for the VL supply J36 VA_HP Selects source of voltage for the VA_HP supply *+1.8V Voltage source is +1.8 V regulator. +2.5V Voltage source is +2.5 V regulator. J25 VA Selects source of voltage for the VA supply *+1.8V Voltage source is +1.8 V regulator. +2.
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DS792DB1 7. CDB43L22 BLOCK DIAGRAM Reset USB µ controller I2C Interface PLL Oscillator (socket) Analog Passthrough Input Speaker Outputs CS43L22 S/PDIF Input (CS8416) FPGA Analog Output (Line + Headphone) Reset Clk/Data SRC (CS8421) PSIA Input Header External System Input Header 19 CDB43L22 Figure 9.
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8. CDB43L22 SCHEMATICS CDB43L22 DS792DB1 Figure 10.
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DS792DB1 21 CDB43L22 Figure 11.
PAGE 22
CDB43L22 DS792DB1 Figure 12.
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DS792DB1 CDB43L22 23 Figure 13.
PAGE 24
9. CDB43L22 LAYOUT CDB43L22 CS43L22 CDB43L22 DS792DB1 Figure 14.
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DS792DB1 25 CDB43L22 Figure 15.
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CDB43L22 DS792DB1 Figure 16.
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DS792DB1 27 CDB43L22 Figure 17.
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DS792DB1 CDB43L22 Figure 18.
PAGE 29
CDB43L22 10.PERFORMANCE PLOTS Test conditions (unless otherwise specified): Measurement bandwidth is 20 Hz to 20 kHz (unweighted); VA=VD=VA_HP=1.8V; Sample Frequency = 48 kHz; HP test load: RL = 16 Ω. +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 d B r d B r -70 A -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 20 50 100 200 500 1k 2k 5k 10k -140 20 20k Hz Figure 19.
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CDB43L22 +0 +0 -5 -10 -10 -15 -20 -20 -30 -25 -40 -30 -35 -50 -40 d B r -45 -50 d B r A -55 A -60 -70 -80 -60 -90 -65 -70 -100 -75 -110 -80 -120 -85 -90 -130 -95 -100 20 50 100 200 500 1k 2k 5k 10k -140 20 20k 50 100 200 500 1k 2k 5k 10k 20k Hz Hz Figure 25. FFT - S/PDIF In to Speaker Out @ 0 dBFS Figure 26. FFT - S/PDIF In to Speaker Out @ -60 dBFS 10 +5 +4.5 5 +4 +3.5 +3 2 +2.5 +2 1 +1.5 +1 d B r +0.5 A -0.5 0.5 % -0 0.2 -1 -1.5 0.1 -2 -2.
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CDB43L22 11.REVISION HISTORY Revision DB1 Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.