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Evaluation Board for the CS43L21

Features

 MUX’d Analog Output

– Stereo RCA Output (w/Optional Load or

LPF)

– Stereo Headphone Jack

– Mono Speaker Driver w/Banana Posts

 8 kHz to 96 kHz S/PDIF Interface

– CS8415 Digital Audio Receiver

 I/O Stake Headers

– External Control Port Accessibility

– External DSP Serial Audio I/O Accessibility

 Independent, Regulated Supplies

 1.8 V to 3.3 V Logic Interface

 Hardware Control

– 11 Pre-Defined Switch Settings

 FlexGUI S/W Control - Windows

Compatible

– Pre-Defined & User-Configurable Scripts

 Layout and Grounding Recommendations

Description

The CDB43L21 evaluation board is an excellent means

for evaluating the CS43L21 DAC. Evaluation requires a

digital signal source, analog analyzer, and power sup-

plies. Optionally, a Windows

PC-compatible computer

may be used to evaluate the CS43L21 in Software

Mode.

System timing can be provided by the CS8415, by the

CS43L21 with supplied master clock, or by an I/O stake

header with a DSP connected.

RCA phono jacks are provided for the CS43L21 analog

outputs. 1/8th inch jacks are also available for head-

phone output. Digital data input is available via RCA

phono or optical connectors to the CS8415.

The Windows software provides a Graphical User Inter-

face (GUI) to make configuration of the CDB43L21

easy. The software communicates through the PC’s se-

rial port/USB to configure the control port registers so

that all the features of the CS43L21 can be evaluated.

The evaluation board may also be configured to accept

external timing and data signals for operation in a user

application during system development.

ORDERING INFORMATION

CDB43L21 Evaluation Board

Analog Output

(Line + Headphone)

Software Mode

Control Port

CS43L21

S/PDIF Input

(CS8415)

Clocks/Data Header

I²C/SPI Header

FPGA

Oscillator

(socket)

Reset

MCLK

Reset

MCLK

Reset

Hardware Mode

Switches

JANUARY '08

DS723DB1

CDB43L21

Summary of content (25 pages)

PAGE 1
CDB43L21 Evaluation Board for the CS43L21 Features Description MUX’d Analog Output The CDB43L21 evaluation board is an excellent means for evaluating the CS43L21 DAC. Evaluation requires a digital signal source, analog analyzer, and power supplies. Optionally, a Windows PC-compatible computer may be used to evaluate the CS43L21 in Software Mode.
PAGE 2
CDB43L21 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 Power ............................................................................................................................................... 4 1.2 Grounding and Power Supply Decoupling ....................................................................................... 4 1.3 FPGA .........................................
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CDB43L21 9. ERRATA ............................................................................................................................................... 25 10. REVISION HISTORY .......................................................................................................................... 25 LIST OF FIGURES Figure 1.General Configuration Tab ............................................................................................................ 8 Figure 2.DAC Volume Controls Tab ...
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CDB43L21 1. SYSTEM OVERVIEW The CDB43L21 evaluation board is an excellent means for evaluating the CS43L21. Digital audio signal interfaces are provided, and an FPGA is used for easily configuring the board. Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 11 provide configuration details. The CDB43L21 schematic set has been partitioned into six pages and is shown in Figures 10 through 15.
PAGE 5
CDB43L21 Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 11 provide configuration details. 1.5 CS8415 Digital Audio Receiver A complete description of the CS8415 receiver (Figure 12 on page 18) and a discussion of the digital audio interface are included in the CS8415 data sheet. The CS8415 converts the input S/PDIF data stream from either the optical or the RCA connector into PCM data for the CS43L21.
PAGE 6
CDB43L21 1.9 Stand-Alone Switches The “FPGA H/W Control” and “CS43L21 H/W Control” switches control all Hardware Mode options. Section 3. “Hardware Mode Control” on page 11 provides a description of each topology. 1.10 Control Port Connectors A graphical user interface is available for the CDB43L21, allowing easy manipulation of each register. This GUI interfaces with the CDB via the RS-232 connector and controls all Software Mode options. Section 2.
PAGE 7
CDB43L21 2. SOFTWARE MODE CONTROL The CDB43L21 may be used with the Microsoft® Windows-based FlexGUI graphical user interface, allowing software control of the CS43L21 and FPGA registers. The latest control software may be downloaded from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows: 1. Download and install the FlexGUI software according to the instructions provided on the Website. 2. Connect and apply power to the +5.0 V binding post. 3.
PAGE 8
CDB43L21 2.1 General Configuration Tab The “General Configuration” tab provides high-level control of signal routing on the CDB43L21. This tab also includes basic controls for the CS43L21 for quickly setting up the CDB43L21 in simple configurations. Status text detailing the CS43L21’s specific configuration is shown in parenthesis or appears directly below the associated control. This text may change depending on the setting of the associated control.
PAGE 9
CDB43L21 2.2 DAC Volume Controls Tab The “DAC Volume Controls” tab provides high-level control of all volume settings in the CS43L21. Status text detailing the CS43L21’s specific configuration is shown in read-only edit boxes, in parenthesis, or it appears directly below the associated control. This text will change depending on the setting of the associated control.
PAGE 10
CDB43L21 2.3 Register Maps Tab The Advanced Register Debug tab provides low-level control of the CS43L21 individual register settings. Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push-button for the desired bit. For byte-wise, the desired hex value can be typed directly into the register address box in the register map. The “FPGA” and “GPIO” tabs may be ignored. Figure 3.
PAGE 11
CDB43L21 3. HARDWARE MODE CONTROL The CDB may be configured without the use of a software control port through the use of two switches, “FPGA H/W Control” and “CS43L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software Mode. The CDB43L21 automatically enters Hardware Mode upon initial power up, when exiting Software Mode, upon termination of the Cirrus FlexGUI software, or by disconnecting the RS-232 serial cable. 3.
PAGE 12
CDB43L21 Oscillator Oscillator CS8415 CS43L21 RMCK (256Fs) MCLK CS8415 CS43L21 RMCK (256Fs) MCLK OLRCK/ OSCLK LRCK/SCLK OLRCK/ OSCLK LRCK/SCLK SDOUT (LJ) SDIN SDOUT (LJ) SDIN I/O Header I/O Header MCLK MCLK LRCK/SCLK LRCK/SCLK SDIN SDIN Figure 4. Routing 1 Figure 5.
PAGE 13
CDB43L21 Oscillator CS8415 CS43L21 RMCK (256Fs) MCLK OLRCK/ OSCLK LRCK/SCLK SDOUT (LJ) SDIN I/O Header MCLK LRCK/SCLK SDIN Figure 8.
PAGE 14
CDB43L21 4. SYSTEM CONNECTIONS CONNECTOR REF INPUT/OUTPUT +5V GND RS232 USB S/PDIF OPTICAL IN S/PDIF COAX IN I/O Header S/W CONTROL MICRO JTAG FPGA JTAG MICRO RESET FPGA PROGRAM H/W BOARD RESET LEFT RIGHT SPEAKER + SPEAKER Headphone Jack J26 J27 J95 J94 OPT1 J61 J5 J109 J110 J78 S4 S2 S1 J19 J20 J72 J73 J11 Input Input Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input Input Input Output Output Output SIGNAL PRESENT +5.
PAGE 15
DS723DB1 6. CDB43L21 BLOCK DIAGRAM Software Mode Control Port I²C/SPI Header Reset MCLK Reset Hardware Mode Switches CS43L21 S/PDIF Input (CS8415) Analog Output (Line + Headphone) FPGA Reset MCLK Oscillator (socket) Reset Clocks/Data Header CDB43L21 15 Figure 9.
PAGE 16
7. CS43L21 SCHEMATICS CDB43L21 DS723DB1 Figure 10.
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DS723DB1 CDB43L21 17 Figure 11.
PAGE 18
CDB43L21 DS723DB1 Figure 12.
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DS723DB1 CDB43L21 19 Figure 13.
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CDB43L21 DS723DB1 Figure 14.
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DS723DB1 CDB43L21 21 Figure 15.
PAGE 22
8. CDB43L21 LAYOUT CDB43L21 CS43L21 CS43L21 CS43L21 CDB43L21 DS723DB1 Figure 16.
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DS723DB1 CDB43L21 23 Figure 17.
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CDB43L21 DS723DB1 Figure 18.
PAGE 25
CDB43L21 9. ERRATA The CDB43L21 currently does not support the +1.8 V and +2.5 V power supply options on header J31 (VL). This header must be set to +3.3 V to ensure correct board operation. This issue is not device related; the allowed voltage levels are specified in the CS43L21 data sheet. 10.REVISION HISTORY Revision DB1 Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.