Manual

10 DS686DB3
CDB4270
2.3 Internal Data Routing
Figure 4 shows the internal data routing topology between the CS4270, CS8416, CS8406 and the DSP
Header. Refer to the FPGA GUI Register Description section of this document for a description of the audio
data routing register settings.
.
CS8406
SDIN
CS4270-FPGA-SDOUT
SDIO[1:0]
CS8416-FPGA-SDOUT
FPGA-SDIN
TXSDIO[1:0]
CS4270
SDIN
SDOUT
DSP Header
SDIN
SDOUT
CS8416
SDOUT
FPGA-HDR-SDOUT
CS4270-SDIN
CS8406-SDIN
FPGA
DUT_SDIO[1:0]
Figure 4. Internal Data Routing