CDB4270 Evaluation Board for CS4270 Features Description Single-Ended Analog Audio Inputs and Outputs CS8416 S/PDIF Digital Audio Receiver Using the CDB4270 is an excellent way to evaluate the CS4270 CODEC. Other equipment required includes analog/digital audio sources/analyzer, a 5V power supply and a Windows-compatible PC for the GUI. Header for External Configuration of CS4270 Header for External DSP Serial Audio I/O 3.
CDB4270 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 5 1.1 Power ............................................................................................................................................... 5 1.2 Grounding and Power Supply Decoupling ........................................................................................ 5 1.3 FPGA .........................................
CDB4270 LIST OF FIGURES Figure 1.ADC THD+N ................................................................................................................................. 7 Figure 2.ADC Dynamic Range .................................................................................................................... 7 Figure 3.Internal Sub-Clock Routing ........................................................................................................... 9 Figure 4.Internal Data Routing ..............
CDB4270 Figure 53.96 kHz, Crosstalk ...................................................................................................................... 34 Figure 54.96 kHz, Impulse Response ....................................................................................................... 34 Figure 55.FFT (192 kHz, 0 dB) ................................................................................................................. 34 Figure 56.FFT (192 kHz, -60 dB) .................................
CDB4270 1. SYSTEM OVERVIEW The CDB4270 evaluation board is an excellent tool for evaluating the CS4270 CODEC. The board features both analog and digital audio interfaces along with an FPGA for data/clk routing and an on-board microprocessor for configuration control. The board is easily configured in Software Mode using the supplied PC-to-DUT USB cable along with the Windows-based GUI configuration software or in Hardware Mode using the on-board dip switches.
CDB4270 1.7 Canned Oscillator Oscillator Y1 provides a system master clock. This clock is routed through the CS8416 and out of the RMCK pin when the S/PDIF input is disconnected (refer to the CS8416 data sheet for details on OMCK operation). To use the canned oscillator as the source of the MCLK signal, remove the S/PDIF input to the CS8416 and configure the CS8416 appropriately. The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with a 12.
CDB4270 Figure 1. ADC THD+N Figure 2.
CDB4270 1.10 Analog Outputs The CS4270 analog outputs are AC-coupled and routed through a single-pole RC Low-Pass filter. 1.11 Control Port A graphical user interface is included with the CDB4270 to allow easy manipulation of the registers in the CS4270 (see the CS4270 data sheet for register descriptions and the “FPGA GUI Register Description” on page 18). The GUI will run on a standard Windows-based PC.
CDB4270 2. FPGA OVERVIEW The FPGA (U11) controls all digital signal routing between the CS4270, CS8406, CS8416 and the DSP I/O Header. The device also generates all of the clock/data driver output enables and S/PDIF device mode controls. The FPGA internal registers can be configured either via the I²C (Software Mode) or via external dip switches (Hardware Mode). When using the CS4270 in Hardware Mode, the FPGA decodes some of these dip-switch settings and generates the CS4270 control signals.
CDB4270 2.3 Internal Data Routing Figure 4 shows the internal data routing topology between the CS4270, CS8416, CS8406 and the DSP Header. Refer to the FPGA GUI Register Description section of this document for a description of the audio data routing register settings. .
CDB4270 2.4 Internal Drivers Figure 5 shows the internal drivers and logic for board level selects/enables and so forth. Refer to the FPGA GUI Register Description section of this document for a description of the board level control register settings. .
CDB4270 2.5 External MCLK Control Several sources for MCLK exist on the CDB4270. The crystal oscillator, Y1, will master the MCLK bus when no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for details on OMCK operation). When S/PDIF data is present at the CS8416 input, the CS8416 generates a master clock whenever its internal PLL is locked to the incoming S/PDIF stream.
CDB4270 3. SOFTWARE MODE The CDB4270 uses a Microsoft Windows-based GUI (download from Cirrus web site), which allows control of the CS4270 and FPGA registers. Interface to the GUI is provided via USB or RS-232 serial connection. Once the appropriate cable is connected between the CDB4270 and the host PC, run “FlexLoader.exe”. The software should automatically detect the board. If a board selection dialog is displayed, select “CDB4270” from the list.
CDB4270 3.2 CDB4270 GUI Brief descriptions of the GUI tab views are provided below. The CDB4270 Controls tab provides high-level control of the CS4270, FPGA (Board Controls) and S/PDIF Tx and Rx devices. The “CS4270 Controls” group affects that device’s register settings. The “Board Controls” group allows the user to select MCLK and sub-clock source/routing as well as CS4270 and CS8406 SDIN sources.
CDB4270 3.3 Register Maps Control Tabs Under this tab are the CS4270, Board Configuration (FPGA) and GPIO tabs. On each tab, register values can be modified bit-wise or byte-wise. For bit-wise modification, click the appropriate push-button for the desired bit. For byte-wise modification, the desired hex value can be typed directly into the register address box in the register map.
CDB4270 Figure 9.
CDB4270 Figure 10.
CDB4270 4. HARDWARE MODE When the Flex GUI is not running on a PC or when the USB or serial port cables are not connected to the CDB4270 from the PC, the board is automatically in Hardware Control Mode. When in this control mode, dip switches S1 and S2 control the board’s functionality. Note: Hardware Mode controls are a subset of Software Mode controls, and some FPGA or CS4270 register bits cannot be changed in Hardware Mode.
CDB4270 5.2 FPGA CODE REVISION ID - ADDRESS 00H 7 REV.7 5.2.1 6 REV.6 5 REV.5 4 REV.4 3 REV.3 2 REV.2 1 REV.1 0 REV.0 Revision Number Bits (Bits 7:0) Function: Identifies FPGA code revision number. REV.7 - REV.4 indicate revision whole number, and REV.3 REV.0 indicate revision decimal number. These register bits are Read-Only. See Table 1. REV.7 REV.6 REV.5 REV.4 REV.3 REV.2 REV.1 REV.0 Revision Number 0 0 0 0 0 0 0 0 Not Used 0 0 0 1 0 0 0 1 Revision 1.
CDB4270 5.3 CS4270 CONTROL - ADDRESS 01H 7 SDIO.1 5.3.1 6 SDIO.0 5 Reserved 4 MCLK 3 DUT_SDIO.1 2 DUT_SDIO.0 1 SUB_CK.1 0 SUB_CK.0 SDOUT Routing to Header (Bits 7:6) Default = 00 Function: These bits control the routing of SDOUT from the CS8416, CS4270 and the Header SDIN to the Header SDOUT. Table 2 shows the available settings. SDIO.1 SDIO.
CDB4270 5.3.4 Subclock Routing (Bits 1:0) Default = 00 Function: These bits select SCLK and LRCK routing to/from the CS4270, CS8416, CS8406 and the Header. Table 5 shows the available settings. SUB_CK.1 SUB_CK.
CDB4270 5.4.2 CS8406 Master/Slave Select (Bit 4) Default = 0 Function: This bit selects CS8406 Master Mode (SCLK, LRCK are outputs) or Slave Mode (SCLK, LRCK are inputs). See Table 7. TX_M/S CS8406 Master/Slave 0 CS8406 Slave Mode 1 CS8406 Master Mode Table 7. CS8406 Master/Slave 5.4.3 CS8406 SDIN Format Select (Bit 3) Default = 0 Function: This bit selects the CS8406 SDIN format. See Table 8. TX_FMT CS8406 SDIN Format 0 24-bit Left-Justified 1 24-bit I²S Table 8. CS8406 SDIN Format 5.4.
CDB4270 5.5 CS8416 RX CONTROL - ADDRESS 03H 7 Reserved 5.5.1 6 RXCLK 5 Reserved 4 RX_M/S 3 RX_FMT 2 Reserved 1 Reserved 0 Reserved CS8416 RMCLK Divider Control (Bit 6) Default = 0 Function: This bit selects the CS8416 RMCLK divider ratio. Table 10. RXCLK CS8416 RMCLK Frequency 0 256 x Fs 1 128 x Fs Table 10. CS8416 RMCLK Frequency 5.5.
CDB4270 6. CDB4270 HARDWARE MODE SETTINGS Schematic-Level Functional Description: When the Flex GUI is not used and there is no serial port communication to the board, all devices are in HW Mode. FPGA SW control is disabled in this condition, and DIP switches S1 and S2 on the CDB4270 set the FPGA Registers to control board functionality. Note that the CS8406 and CS8416 are reset when SW/HW from the microprocessor goes low (going from SW to HW Mode).
CDB4270 Dip Switch (1) Logic State M1, M0, MDIV2, MDIV1 CS4270 Functional S2 0,0,0,0 Sets CS4270 Single Speed MCLK divide by 1 Mode, no de-emphasis, CS8406 OMCLK=256xFs and CS8416 RMCLK=256xFs S2 0,1,0,0 Sets CS4270 Single Speed MCLK divide by 1 Mode, w/de-emphasis, CS8406 OMCLK=256xFs and CS8416 RMCLK=256xFs S2 1,0,0,0 Sets CS4270 Double Speed MCLK divide by 1 Mode, no de-emphasis, CS8406 OMCLK=128xFs and CS8416 RMCLK=128xFs S2 1,0,1,0 Sets CS4270 Double Speed MCLK divide by 2 Mode, no de-emp
CDB4270 7. CDB CONNECTORS, SWITCHES, INDICATORS AND JUMPERS CONNECTOR, SWITCH Reference Designator INPUT/OUTPUT SIGNAL PRESENT +5V J1 Input +5.
CDB4270 8. ADC PERFORMANCE PLOTS +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 d B F S d B F S -70 -80 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 50 100 200 500 1k 2k 5k 10k -150 20 20k 50 100 200 500 1k 2k 5k 10k 20k Hz Hz Figure 11. FFT (-1 dB 48 kHz) Figure 12.
CDB4270 +5 +0 -10 +4 -20 +3 -30 -40 +2 -50 +1 d B F S -60 d B F S +0 -1 -70 -80 -90 -100 -2 -110 -3 -120 -130 -4 -140 -5 20 50 100 200 500 1k 2k 5k 10k -150 20 20k 50 100 200 500 Hz Figure 17. 48 kHz, Frequency Response +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 5k 10k 20k -60 d B F S -70 -80 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 2k Figure 18.
CDB4270 +40 +0 TT T +35 -10 +30 -20 +25 +20 -30 +15 -40 d B F S +10 -50 +5 d B F S -60 +0 -5 -70 -10 -15 -80 -20 -90 -25 -100 -30 -35 -110 -120 -100 -80 -60 -40 -20 -40 -140 +0 dBr -120 -100 -80 -60 -40 -20 +0 dBr Figure 23. 96 kHz, THD+N vs. Level Figure 24.
CDB4270 +0 +0 -10 -10 -20 -30 -20 -40 -30 -50 -40 -60 d B F S d B F S -70 -80 -50 -60 -90 -70 -100 -110 -80 -120 -90 -130 -100 -140 -150 20 50 100 200 500 1k 2k 5k 10k -110 20 20k 50 100 200 500 Hz 1k 2k 5k 10k 20k Hz Figure 29. FFT (192 kHz, No Input) Figure 30. 192 kHz, THD+N vs.
CDB4270 9.
CDB4270 +40 +5 +35 +4 +30 +25 +3 +20 +2 +15 +10 +1 d B r +5 A -5 d B r +0 A -10 -15 +0 -1 -2 -20 -3 -25 -30 -4 -35 -40 -140 -120 -100 -80 -60 -40 -20 -5 20 +0 50 100 200 500 dBFS 1k 2k 5k 10k 20k Hz Figure 41. 48 kHz, Fade-to-Noise Linearity Figure 42. 48 kHz, Frequency Response +0 2 -10 1.75 TTTTT TTTTTTTTTT TTTTTT TTTTT T TTTT 1.5 -20 1.25 -30 1 -40 750m -50 500m -60 d B r 250m -70 V -80 0 -250m A -90 -500m -100 -750m -110 -1 -120 -1.
CDB4270 +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 d B r d B r -70 A -70 -80 -80 A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 20 50 100 200 500 1k 2k 5k 10k 20k 20k 40k 60k Figure 47. FFT (96 kHz, No Input) 100k 120k Figure 48.
CDB4270 +0 2 -10 1.75 TTTTT TT T TTT TTTT T TT TTTT TTT TT TTTT 1.5 -20 1.25 -30 1 -40 750m -50 500m -60 d B r 250m -70 0 V -80 -250m A -90 -500m -100 -750m -110 -1 -120 -1.25 -130 -1.5 -140 -1.75 -150 20 50 100 200 500 1k 2k 5k 10k -2 0 20k 250u 500u Figure 53.
CDB4270 +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 d B r d B r -50 -50 -60 -60 A A -70 -70 -80 -80 -90 -90 -100 -100 -110 20 50 100 200 500 1k 2k 5k 10k -110 -120 20k -100 -80 -60 -40 -20 +0 dBFS Hz Figure 59. 192 kHz, THD+N vs. Input Freq Figure 60. 192 kHz, THD+N vs.
10.CDB BLOCK DIAGRAM Power Figure 23 Hardware Setup USB/Serial Control Port CS8406 S/PDIF Output I2C/SPI Header Figure 19 Figure 24 ANALOG INPUT Figure 23 Single-Ended Input Clocks/Data Figure 17 CS4270 MCLK BUS Figure 20 Hardware Setup Clocks /Data FPGA Figure 22 ADC/DAC Clocks & Data CS8416 S/PDIF Input ADC/DAC Clocks/ Data Osc.
DS686DB3 11.CDB SCHEMATICS Figure 66.
CDB4270 DS686DB3 Figure 67.
DS686DB3 39 CDB4270 Figure 68.
Figure 69.
DS686DB3 Figure 70.
CDB4270 DS686DB3 Figure 71.
DS686DB3 CDB4270 43 Figure 72.
CDB4270 DS686DB3 Figure 73.
DS686DB3 45 CDB4270 Figure 74.
12.CDB LAYOUT Figure 75.
DS686DB3 Figure 76.
CDB4270 DS686DB3 Figure 77.
CDB4270 13. CHANGES MADE TO REV. B BOARD 13.1 Modifications (Done by Cirrus Logic) Note: DS686DB3 There is no rework necessary when CS4270 C0 parts are installed on the Rev. B board. See CDB Data Sheet DS686DB2 when B0 parts are installed on the Rev. B board or DS686DB1 when A0 parts are installed on the Rev. A board. Also reference the Rev. A0, B0, and C0 chip Errata at http://www.cirrus.com/en/support. Select Errata from the product information categories shown.
CDB4270 14. REVISION HISTORY Revision Changes DB1 Initial Release: Applies to A Assy. (A2 PL). DB2 This Revision is for the B Assy. (B2 PL). Updates for USB port use, new GUI graphics, new schematics, new rework information, new layout graphics and added performance plots. Removed Rev. A/A1 (PL) references, schematics, layout graphics and rework.
