CDB4265
18 DS657DB1
7. CDB BLOCK DIAGRAM
CS4265
Passive Input Filter
Active Input Filter
Header
Microphone Input
S/PDIF Output Circuits
Canned
Oscillator
Control Port Interface
Test Points
M
U
X
Master Clock
Passive Output Filter
Active Output Filter
CS8416
FPGA
Sub-clocks and Data
Figure 4. Block Diagram
