Owner's manual

CDB4245
DS656DB1 3
LIST OF FIGURES
Figure 1. CDB4245 Controls Tab.................................................................................................... 7
Figure 2. S/PDIF I/O Controls Tab.................................................................................................. 8
Figure 3. Register Maps Tab........................................................................................................... 9
Figure 4. Block Diagram................................................................................................................ 17
Figure 5. CS4245.......................................................................................................................... 18
Figure 6. Analog Inputs................................................................................................................. 19
Figure 7. Analog Outputs .............................................................................................................. 20
Figure 8. S/PDIF I/O...................................................................................................................... 21
Figure 9. Control Port.................................................................................................................... 22
Figure 10. FPGA ........................................................................................................................... 23
Figure 11. Discrete Clock Routing and Level Shifting................................................................... 24
Figure 12. Power........................................................................................................................... 25
Figure 13. Silk Screen................................................................................................................... 26
Figure 14. Topside Layer .............................................................................................................. 27
Figure 15. Bottom side Layer........................................................................................................ 28
LIST OF TABLES
Table 1. MCLK2 Source................................................................................................................ 12
Table 2. MCLK1 Source................................................................................................................ 12
Table 3. DAC Subclock Source..................................................................................................... 13
Table 4. ADC Subclock Source..................................................................................................... 13
Table 5. SDIN1 Source ................................................................................................................. 14
Table 6. CS8406 SDIN Source .....................................................................................................14
Table 7. System Connections ....................................................................................................... 15
Table 8. System Jumper Settings .................................................................................................16
Table 9. Revision History .............................................................................................................. 29