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Cirrus Logic, Inc.

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CDB4245

Evaluation Board for CS4245

Features

z Single-ended Analog Inputs

z Single-ended Analog Outputs

z CS8406 S/PDIF Digital Audio Transmitter

z CS8416 S/PDIF Digital Audio Receiver

z Independent ADC and DAC Clock Domains

z Header for Optional External Software

Configuration of CS4245

z Header for External PCM Serial Audio I/O

z 3.3 V Logic Interface

z Pre-defined Software Scripts

z Demonstrates Recommended Layout and

Grounding Arrangements

z Windows

Compatible Software Interface

to Configure CS4245 and Inter-board

Connections

ORDERING INFORMATION

CDB4245 Evaluation Board

Description

The CDB4245 evaluation board is an excellent means

for evaluating the CS4245 CODEC. Evaluation requires

an analog/digital signal source and analyzer, and power

supplies. A Windows

PC compatible computer must be

used to evaluate the CS4245.

System timing for the I²S, Left-Justified and Right-Justi-

fied interface formats can be provided by the CS4245,

the CS8416, the CS8406, or by a PCM I/O stake header

with an external source connected.

RCA phono jacks are provided for the CS4245 analog in-

puts and outputs. Digital data I/O is available via RCA

phono or optical connectors to the CS8416 and CS8406.

The Windows

software provides a GUI to make config-

uration of the CDB4245 easy. The software

communicates through the PC’s serial port to configure

the control port registers so that all features of the

CS4245 can be evaluated. The evaluation board may

also be configured to accept external timing and data

signals for operation in a user application during system

development.

CS4245

FPGA

CS8416 CS8406

Passive Input Filter

Header

Active Input Filter

Header

Microphone Input

Passive Output Filter

Active Output Filter

Canned

Oscillator

Canned

Oscillator

Control Port Interface

Test Points

CS8416 CS8406

Master Clock Master Clock

Sub-clocks and Data

FEB ‘05

DS656DB1

Summary of content (29 pages)

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CDB4245 Evaluation Board for CS4245 Features Description z The CDB4245 evaluation board is an excellent means for evaluating the CS4245 CODEC. Evaluation requires an analog/digital signal source and analyzer, and power supplies. A Windows® PC compatible computer must be used to evaluate the CS4245.
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CDB4245 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................... 4 1.1 Power ................................................................................................................................. 4 1.2 Grounding and Power Supply Decoupling ......................................................................... 4 1.3 CS4245 Audio CODEC ......................................................................
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CDB4245 LIST OF FIGURES Figure 1. CDB4245 Controls Tab.................................................................................................... 7 Figure 2. S/PDIF I/O Controls Tab .................................................................................................. 8 Figure 3. Register Maps Tab........................................................................................................... 9 Figure 4. Block Diagram............................................................
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CDB4245 1. SYSTEM OVERVIEW The CDB4245 evaluation board is an excellent means for evaluating the CS4245 CODEC. Analog and digital audio signal interfaces are provided, an on-board FPGA is used for easily configuring the evaluation platform, and a 9-pin serial cable is included for use with the supplied Windows® configuration software. The CDB4245 schematic set is shown in Figures 5 through 12. 1.1 Power Power must be supplied to the evaluation board through the red +5.0 V binding post.
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CDB4245 1.6 FPGA The FPGA handles both clock and data routing on the CDB4245. Clock and data routing selections made via the CDB4245 Controls tab in the GUI will be handled by the FPGA with no user intervention required. For advanced information regarding the internal registers and operation of the FPGA, see sections 5 and 6 beginning on page 11. 1.7 Canned Oscillators Two canned oscillators, Y1 and Y2, are available to provide a master clock source to the CDB4245.
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CDB4245 1.12 USB Control Port The USB control port connector (J37) is currently unavailable. 2. SYSTEM CLOCKING The CDB4245 implements two discrete clocking domains. One discrete domain services Serial Audio Port 1 of the CS4245, and the other discrete domain services Serial Audio Port 2 of the CS4245. The two clock domains may operate independently, or may be tied together.
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CDB4245 4. PC SOFTWARE CONTROL The CDB4245 is shipped with a Microsoft Windows® based graphical user interface which allows control over the CS4245, CS8416, CS8406, and FPGA. The board control software communicates with the CDB4245 over the RS232 interface using the PC’s COM1 port. To use the board control software, the contents of the included CD-ROM should first be copied to a directory on the PC’s local disk. If applied, the Read Only attribute should be removed from all files.
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CDB4245 4.2 S/PDIF I/O Controls Tab When the CDB4245 is configured to make use of the CS8416 S/PDIF receiver or CS8406 S/PDIF transmitter, these devices must be configured for proper operation. The S/PDIF I/O Controls tab provides a highlevel intuitive interface to the most common configuration options of the CS8416 and CS8406. Figure 2.
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CDB4245 4.3 Register Maps Tab The Register Maps tab provides low level control over the register level settings of the CS4245, CS8416, CS8406, and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push button for the desired bit. For byte-wise, the desired hex value can be typed directly in the register address box in the register map. Figure 3. Register Maps Tab 4.
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CDB4245 4.4.2 SPDIF Recovered Clock - SPDIF to DAC & ADC to SPDIF Using the pre-configured script file named “SPDIF Recovered Clock - SPDIF to DAC & ADC to SPDIF.txt”, an analog input signal applied to channel 1 of the CS4245 input multiplexer will be digitized by the ADC, transmitted in S/PDIF format by the CS8406. A S/PDIF input signal will be converted to analog by the CS4245 DAC and output through the passive output filter and RCA jacks.
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CDB4245 5. FPGA REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr 01h 02h Function Code Rev. ID MCLK Source 7 6 5 4 3 2 1 0 Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0 x x x x x x x x MCLK2.1 MCLK2.0 Reserved Reserved MCLK1.1 MCLK1.0 1 0 0 0 0 0 DAC1 DAC0 Reserved Reserved ADC1 ADC0 0 1 0 0 0 1 Reserved Reserved Reserved Reserved SDIN1 SDIN0 0 0 0 0 0 0 CS8406.1 CS8406.
PAGE 12
CDB4245 6. FPGA REGISTER DESCRIPTION 6.1 CODE REVISION ID - ADDRESS 01H 7 Rev7 6 Rev6 5 Rev5 4 Rev4 3 Rev3 2 Rev2 1 Rev1 0 Rev0 1 MCLK1.1 0 MCLK1.0 Function: Identifies the revision of the FPGA code. This register is Read-Only. 6.2 MCLK SOURCE CONTROL - ADDRESS 02H 7 Reserved 6.2.1 6 Reserved 5 MCLK2.1 4 MCLK2.0 3 Reserved 2 Reserved MCLK2 SOURCE (BITS 5:4) Default = 10 Function: These bits select the source of the CS4245 MCLK2 signal. Table 1 shows the available settings. Table 1.
PAGE 13
CDB4245 6.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H 7 Reserved 6.3.1 6 Reserved 5 DAC1 4 DAC0 3 Reserved 2 Reserved 1 ADC1 0 ADC0 DAC SUBCLOCK SOURCE (BITS 5:4) Default = 01 Function: These bits select the source of the CS4245 SCLK2 and LRCK2 signals. Table 3 shows the available settings. Table 3.
PAGE 14
CDB4245 6.4 CS4245 SDIN SOURCE CONTROL - ADDRESS 04H 7 Reserved 6 Reserved 6.4.1 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 SDIN1 0 SDIN0 SDIN SOURCE (BITS 1:0) Default = 00 Function: These bits select the source of the CS4245 SDIN1 signal. Table 5 shows the available settings. Table 5. SDIN1 Source 6.5 SDIN1 SDIN0 SDIN Source 0 0 CS8416 SDOUT 0 1 CS4245 SDOUT 1 0 SDIN from Header 1 1 Reserved TRANSMITTER SDIN SOURCE CONTROL - ADDRESS 05H 7 Reserved 6 Reserved 6.5.
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CDB4245 7. CDB CONNECTORS, JUMPERS, AND SWITCHES CONNECTOR Reference Designator INPUT/OUTPUT SIGNAL PRESENT +5V J1 Input +5.
PAGE 16
CDB4245 JUMPER PURPOSE POSITION J3 Selects the source of voltage for the VLC supply. +1.8 V +2.5 V +3.3 V +5 V* Voltage source is +1.8 V regulator. Voltage source is +2.5 V regulator. Voltage source is +3.3 V regulator. Voltage source is +5 V regulator. J4 Selects the source of voltage for the VD supply +3.3 V +5 V* Voltage source is +3.3 V regulator. Voltage source is +5 V regulator. J5 Selects the source of voltage for the VLS supply. +1.8 V +2.5 V +3.3 V +5 V* Voltage source is +1.
PAGE 17
DS656DB1 CS8406 CS8416 Figure 4. Block Diagram Sub-clocks and Data FPGA CS8406 Header Master Clock Test Points Header Control Port Interface CS4245 Active Output Filter Canned Oscillator CS8416 M U X Passive Output Filter Canned Oscillator Master Clock Microphone Input Active Input Filter Passive Input Filter CDB4245 8.
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CDB4245 Figure 5. CS4245 9.
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Figure 6.
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Figure 7.
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Figure 8.
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Figure 9.
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Figure 10.
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Figure 11.
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Figure 12.
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CDB4245 Figure 13. Silk Screen 10.
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Figure 14.
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Figure 15.
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CDB4245 11. REVISION HISTORY Revision Date DB1 February 2005 Changes Initial Release Table 9. Revision History Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.