User Manual

CDB42448
30 DS648DB2
7. CDB BLOCK DIAGRAM
CS42448
CS8416
S/PDIF
Input
y Differential to
Single-Ended Output
y Passive Filter on
each Leg
y Single-Ended to
Differential Input
Serial Control Port
FPGA
CS8406
S/PDIF
Output
DSP H EADE R
CS5341
Osc.
ANALOG INPUT
ANALOG OUTPUT
y Single-Ended
Input
AUXILIARY
ANALOG INPUT
MCLK Divided
Clocks
/Data
Hardware
Setup
MCLK B US
ADC/DAC Clocks & Data
ADC/DAC
Clocks/
Data
Clocks/Data
I
2
C/SPI Header
Power
Figure 8. Block Diagram
Figure 9 on page 31
Figure 10 on page 32
Figure 11 on page 3 3
Figure 11 on page 33
Figure 14 on page 36
Figure 16 on page 38
Figure 12 on page 34
Figure 18 on page 40
Figure 16 on page 38
Figure 17 on page 39
Figure 16 on page 38