User Manual

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CDB42448

DS648DB2 3

LIST OF FIGURES

Figure 1. Advanced Register Tab - CS42448 ................................................................................. 7

Figure 2. Advanced Register Tab - FPGA ...................................................................................... 8

Figure 3. Internal Sub-Clock Routing ............................................................................................10

Figure 4. Internal Data Routing..................................................................................................... 11

Figure 5. TDMer ............................................................................................................................ 12

Figure 6. External MCLK Control .................................................................................................. 13

Figure 7. Bypass FPGA Control.................................................................................................... 14

Figure 8. Block Diagram................................................................................................................ 30

Figure 9. CS42448 ........................................................................................................................ 31

Figure 10. FPGA ........................................................................................................................... 32

Figure 11. S/PDIF Input & Output ................................................................................................. 33

Figure 12. Control Port.................................................................................................................. 34

Figure 13. Buffers - FPGA Bypass................................................................................................35

Figure 14. Buffers - DSP Routing.................................................................................................. 36

Figure 15. Analog Inputs ............................................................................................................... 37

Figure 16. Auxiliary Input .............................................................................................................. 38

Figure 17. Analog Outputs ............................................................................................................ 39

Figure 18. Power........................................................................................................................... 40

Figure 19. Silk Screen................................................................................................................... 41

Figure 20. Topside Layer .............................................................................................................. 42

Figure 21. Bottom side Layer ........................................................................................................ 43

LIST OF TABLES

Table 1. Data to SDIN4 ................................................................................................................. 17

Table 2. Data to SDIN3 ................................................................................................................. 17

Table 3. Data to SDIN2 ................................................................................................................. 17

Table 4. Data to SDIN1 ................................................................................................................. 18

Table 5. Clocks to DAC................................................................................................................. 18

Table 6. Clocks to ADC................................................................................................................. 19

Table 7. Data to CS8406............................................................................................................... 19

Table 8. Data to DSP .................................................................................................................... 24

Table 9. System Connections ............. .... ... ... ... ... .... ... ... ... .......................... ... .... ... ... ... .... ... ............ 28

Table 10. Jumper Settings ..... .... ... ... ... .......................... ... .... ... ... ... .... ... ... ... ... .... ............................ 29

Table 11. Revision History ......................... ... ... ... .... ... ... ... .... ... ... .......................... ... ... .... ... ... ......... 44