User Manual

CDB42448

14 DS648DB2

3.6 Bypass Control - Advanced

The DSP clocks and data may be routed through buffers directly to the CS42448, bypassing

the FPGA. This configuration may be desired for more stringent timing requirements at higher

clock speeds. See register “Bypass Control (address 06h)” on page 22. These bits are only

accessible through the Advanced tab of the Cirrus Logic FlexGui software.

NOTE: To avoid contention with the FPGA, set the clock direction for the FPGA appropriately: The FPGA->DAC

and FPGA->ADC bits in register 03h and 07h must be set to ‘1’b.

DSP Header

DSP_ADC.LRCK/

SCLK

DSP_DAC.LRCK/

SCLK

DSP.SDIN1-3

DSP.SDOUT1-4

CS42448

ADC.LRCK

/SCLK

DAC.LRCK

/SCLK

SDOUT1-3

SDIN1-4

FPGA – Bypass Control

DSP->DAC

DSP->ADC

DAC->DSP

ADC->DSP

SDOUT->DSP

DSPDATA->DAC

NOTE: FPGA->DSPb bits in

Reg 07h must be disa bled

to avoid bus co ntention.

NOTE: FPGA->ADC/

DACb bits in Reg 03h

must be disabl ed to avoid

bus contention.

Figure 7. Bypass FPGA Control