User Manual

ManualsBrandsCirrus Logic ManualsHardwareCDB42448

Cirrus Logic, Inc.

www.cirrus.com

CDB42448

Evaluation Board For CS42448

Features

z Single-ended/Single-ended to Differential

Analog Inputs

z Single-ended/Differential to Single-ended

Analog Outputs

z CS8406 S/PDIF Digital Audio Transmitter

z CS8416 S/PDIF Digital Audio Receiver

z Header for Optional External Software

Configuration of CS42448

z Header for External DSP Serial Audio I/O

z 3.3 V Logic Interface

z Pre-defined Software Scripts

z S/PDIF-to-TDM Conversion for Easy

Evaluation of the TDM Digital Interface

z Demonstrates Recommended Layout and

Grounding Arrangements

z Windows

Compatible Software Interface to

Configure CS42448 and Inter-board

Connections

ORDERING INFORMATION

CDB42448 Evaluation Board

Description

The CDB424 48 evaluati on board is an excellent m eans

for evaluating the CS42448 CODEC. Evaluation re-

quires an analog/digital sign al source and analyzer, and

power supplies. A Windows

PC compatible computer

must be used to evaluate the CS42448.

System timing for the I²S, Left-Justified and Right-Justi-

fied interface formats can be provided by the CS42448,

by the CS8416, or by a DSP I/O stake header with a DSP

connected. System timing for TDM mode is provided by

an FPGA using clocks derived from the CS8416 or DSP

I/O header.

RCA phono jacks are provided for the CS42448 analog

inputs and outputs. Digital data I/O is available via RCA

phono or optical connectors to the CS8416 and CS8406.

The Windows

software provides a GUI to make config-

uration of the CDB42448 easy. The software

communicates through the PC’s serial port to configure

the control port registers so that all features of the

CS42448 can be evaluated. The evaluation board may

also be configured to accept external timing and data

signals for operation in a user application during system

development.

CS42448

CS8416

S/PDIF

Input

y Differential to

Single-Ended

Output

y Single-Ended

Output

y Single-Ended to

Differential Input

y Single-Ended

Input

Serial Control Port

FPGA

CS8406

S/PDIF

Output

DSP HEADER

CS5341

Osc.

ANAL OG INPUT

ANALOG OUTPUT

y Single-Ended

Input

AUXILIARY

ANAL OG INPUT

MCLK Divided

Clocks

/Data

Hardware

Setup

MCLK BUS

ADC/DAC Clocks & Data

ADC/DAC

Clocks/

Data

Clocks/Data

C/SPI Header

OCT ‘04

DS648DB2

Summary of content (44 pages)

PAGE 1
CDB42448 Evaluation Board For CS42448 Features Description z Single-ended/Single-ended to Differential Analog Inputs z Single-ended/Differential to Single-ended Analog Outputs z CS8406 S/PDIF Digital Audio Transmitter z CS8416 S/PDIF Digital Audio Receiver z Header for Optional External Software Configuration of CS42448 z Header for External DSP Serial Audio I/O z 3.
PAGE 2
CDB42448 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................... 4 1.1 Power ................................................................................................................................. 4 1.2 Grounding and Power Supply Decoupling ......................................................................... 4 1.3 FPGA ...................................................................................
PAGE 3
CDB42448 LIST OF FIGURES Figure 1. Advanced Register Tab - CS42448 ................................................................................. 7 Figure 2. Advanced Register Tab - FPGA ...................................................................................... 8 Figure 3. Internal Sub-Clock Routing ............................................................................................ 10 Figure 4. Internal Data Routing ....................................................................
PAGE 4
CDB42448 1. SYSTEM OVERVIEW The CDB42448 evaluation board is an excellent means for evaluating the CS42448 CODEC. Analog and digital audio signal interfaces are provided, an FPGA used for easily configuring the board and a 9-pin serial cable for use with the supplied Windows® configuration software. The CDB42448 schematic set has been partitioned into 10 pages and is shown in Figures 9 through 18. 1.1 Power Power must be supplied to the evaluation board through the +5.0 V, +12.0 V and -12.
PAGE 5
CDB42448 clock on the OMCK input pin, and can operate in either the Left-Justified or I²S interface format. Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of the Cirrus Logic FlexGUI software. Refer to register “CS8406 Control (address 04h)” on page 19 for configuration settings. 1.
PAGE 6
CDB42448 Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of the Cirrus Logic FlexGUI software. Refer to register “DSP Header Control (address 07h)” on page 24 for configuration settings The 12-pin, 3 row header, J11, allows the user bidirectional access to the SPI/I2C control signals by simply removing all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable to the “EXTERNAL” position.
PAGE 7
CDB42448 2. SOFTWARE MODE The CDB42448 is shipped with a Microsoft Windows® based GUI, which allows control over the CS42448 and FPGA registers. Interface to the GUI is provided using an RS-232 serial cable. Once the appropriate cable is connected between the CDB42448 and the host PC, load “FlexLoader.exe” from the CDB42448 directory. Once loaded, all registers are set to their default reset state.
PAGE 8
CDB42448 Figure 2.
PAGE 9
CDB42448 3. FPGA SYSTEM OVERVIEW The FPGA (U14) controls all digital signal routing between the CS42448, CS8406 CS8416, CS5341 and the DSP I/O Header. For easy evaluation of the TDM interface format of the CS42448, the FPGA will copy stereo PCM data from either the CS8416 or DSP I/O Header onto one data line at a 256Fs data rate. It will in turn de-multiplex the TDM data from the CS42448 and output stereo channel pairs to the CS8406. 3.1 FPGA Setup Sections 3.2 to 3.
PAGE 10
CDB42448 3.2. Internal Sub-Clock Routing The graphical description below shows the internal clock routing topology between the CS42448, CS8416, CS8406 and DSP Header. Refer to registers “CODEC Clock Control (address 03h)” on page 18, “CS8406 Control (address 04h)” on page 19 and “CS8416 Control (address 05h)” on page 21 for configuration settings. CS8416 LRCK M/S CS8416 LRCK AUX/DAC DAC LRCK AUX LRCK SCLK CS8416 SCLK CS42448 DAC SCLK ADC_MUX[1:0] ADC.
PAGE 11
CDB42448 3.3. Internal Data Routing The graphical description below shows the internal data routing topology between the CS42448, CS8416, CS8406 and DSP Header. Refer to registers “CODEC SDINx Control (address 02h)” on page 17, “CS8406 Control (address 04h)” on page 19 and “DSP Header Control (address 07h)” on page 24 for configuration settings.
PAGE 12
CDB42448 3.4. Internal TDM Conversion, MUXing and Control (TDMer) The graphical description below shows the routing topology of the TDM converter between the CS42448, CS8416, CS8406 and DSP Header. Refer to register “TDM Conversion (address 01h)” on page 16 for configuration settings. The TDMer allows the user to easily evaluate the CS42448 in the TDM digital interface format. A 256Fs clock and an FS pulse is derived from either the CS8416 or DSP Header.
PAGE 13
CDB42448 3.5 External MCLK Control Several sources for MCLK exist on the CDB42448. The crystal oscillator, Y1, will master the MCLK bus when no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for details on OMCK operation). This signal will be driven directly out the CS8416. The CS8416 will generate a master clock whenever its internal PLL is locked to the incoming S/PDIF stream.
PAGE 14
CDB42448 3.6 Bypass Control - Advanced The DSP clocks and data may be routed through buffers directly to the CS42448, bypassing the FPGA. This configuration may be desired for more stringent timing requirements at higher clock speeds. See register “Bypass Control (address 06h)” on page 22. These bits are only accessible through the Advanced tab of the Cirrus Logic FlexGui software.
PAGE 15
CDB42448 4. FPGA REGISTER QUICK REFERENCE Function 7 6 01h TDM Conver- DSP/CS8416 OUT1/OUT2 sion p 16 default 02h CODEC SDINx Control p 17 default 03h CODEC Clock Control p 18 default 04h CS8406 Control p 19 default 05h CS8416 Control p 21 default 06h Bypass Control p 22 default 07h DSP Header Control p 24 default 08h CS5341/Misc Control p 26 default DS648DB2 0 0 5 4 3 2 1 0 OUT1/OUT3 OUT1/OUT4 Reserved Reserved Reserved PDN_TDMer 0 0 0 0 0 0 SDIN4.MUX1 SDIN4.
PAGE 16
CDB42448 5. FPGA REGISTER DESCRIPTION All registers are read/write. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. 5.1 TDM CONVERSION (ADDRESS 01H) 7 6 5 4 3 2 1 0 DSP/CS8416 OUT1/OUT2 OUT1/OUT3 OUT1/OUT4 Reserved Reserved Reserved PDN_TDMer 5.1.
PAGE 17
CDB42448 5.2 CODEC SDINX CONTROL (ADDRESS 02H) 7 6 5 4 3 2 1 0 SDIN4.MUX1 SDIN4.MUX0 SDIN3.MUX1 SDIN3.MUX0 SDIN2.MUX1 SDIN2.MUX0 SDIN1.MUX1 SDIN1.MUX0 5.2.1 SDIN4 MUX(SDIN4.MUX) Default = 11 SDIN4.MUX[1:0] 00 01 10 11 Data Selection CS8416 SDOUT DSP SDOUT1 DSP SDOUT4 ADC_SDOUT1 Table 1. Data to SDIN4 Function: This MUX selects the data lines from the CS8416, DSP Header, and the ADC (see Figure 4 on page 11). 5.2.2 SDIN3 MUX(SDIN3.MUX) Default = 11 SDIN3.
PAGE 18
CDB42448 5.2.4 SDIN1 MUX(SDINX.MUX) Default = 10 SDIN1.MUX[1:0] 00 01 10 11 Data Selection CS8416 SDOUT DSP_ SDOUT1 ADC_SDOUT1 TDM Stream Table 4. Data to SDIN1 Function: This MUX selects the data lines from the CS8416, DSP Header, the ADC and the TDM Stream from the TDMer (see Figure 4 on page 11). 5.3 CODEC CLOCK CONTROL (ADDRESS 03H) 7 6 5 4 3 2 1 0 Reserved Reserved DAC.CLK_ MUX1 DAC.CLK_ MUX0 FPGA->DAC ADC.CLK_ MUX1 ADC,CLK_ MUX0 FPGA->ADCCODEC 5.3.1 DAC CLOCK MUX (DAC.
PAGE 19
CDB42448 5.3.3 ADC MUX (ADC.CLK_MUX) Default = 11 ADC.CLK_ MUX[1:0] Clock Selection CS8416 DAC DSP ADC TDMer 00 01 10 11 Table 6. Clocks to ADC Function: This MUX selects the sub-clock lines from the CS8416, DAC, DSP Header and the sub-clocks from the TDMer internal to the FPGA (see Figure 3 on page 10). 5.3.
PAGE 20
CDB42448 MUX[2:0] 100 101 110 111 Data Selection ADC1 (from ADC_SDOUT1) ADC2 (from ADC_SDOUT1) ADC3 (from ADC_SDOUT1) EXT_ADC (from ADC_SDOUT1) Table 7. Data to CS8406 Function: This MUX selects the data lines from the ADC’s and the external ADC. The first 4 selections shown in Table 7 comes directly from the data output lines. The last 4 selections are de-multiplexed from the TDM stream of SDOUT1 (see Figure 5 on page 12). 5.4.
PAGE 21
CDB42448 5.5 CS8416 CONTROL (ADDRESS 05H) 7 6 5 4 3 2 1 0 Reserved Reserved AUX/DAC RST M/S 128/256 Fs I²S/LJ RMCK_Master 5.5.1 AUX OR DAC CLOCK SELECTION (AUX/DAC) Default = 1 0 - DAC Sub-Clocks to CS8416 1 - AUX Sub-Clocks to CS8416 Function: Selects the clock source for the CS8416 when in slave mode (see Figure 3 on page 10). 5.5.
PAGE 22
CDB42448 5.5.5 LEFT-JUSTIFIED OR I²S INTERFACE FORMAT (I²S/LJ) Default = 0 0 - Left-Justified 1 - I²S Function: Selects either I²S or Left Justified interface format for the CS8416. Pin 6 (RST bit) is held low for 300 µs whenever this bit changes. 5.5.6 RMCK MASTERS MCLK BUS (RMCK_MASTER) Default = 0 0 - Enabled 1 - Disabled Function: Enables/disables the external MCLK output buffer on the MCLK bus (see Figure 6 on page 13). 5.
PAGE 23
CDB42448 routes the FPGA data to the DSP. Refer to schematic Figure 14 on page 36. 5.6.3 ADC TO AUX SDIN (CS5341->AUX) Default = 0 0 - Enable 1 - Disable Function: This bit toggles a control line for the external data buffer to route the external ADC Data directly to the AUX_SDIN port. When disabled, the FPGA will route the CS8416 SDOUT to the AUX_SDIN port. 5.6.
PAGE 24
CDB42448 This bit toggles a control line for the external clock buffer to route the DSP clocks directly to the ADC serial port (see Figure 7 on page 14). 5.7 DSP HEADER CONTROL (ADDRESS 07H) 7 6 5 4 3 Reserved Reserved DATA_MUX2 DATA_MUX1 DATA_MUX0 5.7.1 2 1 FPGA->DSPDAC FPGA->DSPADC 0 MCLK_M/S DATA MUX(DATA_MUX[2:0]) Default = 000 MUX[2:0] 000 001 010 011 100 101 110 111 DSP Data Selection DSP.SDIN1 DSP.
PAGE 25
CDB42448 page 10). 5.7.4 DSP MCLK (MCLK_M/S) Default = 0 0 - DSP MCLK is a slave to the MCLK bus. 1 - DSP MCLK masters MCLK bus. Function: Enables/disables the external DSP MCLK output buffer on the MCLK bus.
PAGE 26
CDB42448 5.8 CS5341 AND MISCELLANEOUS CONTROL (ADDRESS 08H) 7 6 5 4 3 2 1 0 Reserved Reserved INT.MCLK_ DIV INT.DIV_ 1.5/2 ‘41_MCLK_ DIV ‘41_DIV_ 1.5/2 ‘41_I²S/LJ ‘41_RST 5.8.1 INT MCLK DIVIDE (1.5/2.0 DIVIDE) Default = 0 0 - Disabled 1 - Enabled Function: Enables/disables the internal (1.5 or 2.0) divide circuitry for MCLK. 5.8.2 1.5 OR 2.0 MCLK DIVIDE (1.5/2.0 DIVIDE) Default = 0 0 - Divide by 1.5 1 - Divide by 2.0 Function: Divides the internal MCLK by 1.5 or 2 to all internal logic.
PAGE 27
CDB42448 Function: Selects either I²S or Left Justified interface format for the CS5341. Reset to the CS5341 is toggled. 5.8.6 RESET (‘41_RST) Default = 1 0 - CS5341 is held in reset 1 - CS5341 is taken out of reset Function: This bit toggles pin 30 of the FPGA and is held low for 300 µs upon FPGA initialization. It will also be held low for 300 µs whenever register 08h[1] changes.
PAGE 28
CDB42448 6. CDB CONNECTORS AND JUMPERS CONNECTOR Reference Designator INPUT/OUTPUT SIGNAL PRESENT +5V J2 Input +5.0 V Power Supply +12V J5 Input +12.0 V Power Supply -12V J4 Input -12.
PAGE 29
CDB42448 JUMPER PURPOSE POSITION FUNCTION SELECTED J1 Selects source of voltage for the VA supply +3.3V *+5V AIN1(J26) Selects the negative leg of the single-ended to differential input circuit in differential mode, or a VA/2 bias in single-ended mode. *DIFF IN SINGLE IN Inverted signal from AIN1 input VA/2 voltage bias AIN2(J23) Selects the negative leg of the single-ended to differential input circuit in differential mode, or a VA/2 bias in single-ended mode.
PAGE 30
Osc. Figure 11 on page 33 CS8416 S/PDIF Input Figure 11 on page 33 CS8406 S/PDIF Output FPGA Figure 10 on page 32 MCLK BUS Figure 14 on page 36 DSP HEADER Clocks /Data Hardware Setup Clocks/Data ADC/DAC Clocks & Data I2C/SPI Header Figure 8.
PAGE 31
CDB42448 Figure 9. CS42448 8.
PAGE 32
Figure 10.
PAGE 33
Figure 11.
PAGE 34
Figure 12.
PAGE 35
Figure 13.
PAGE 36
Figure 14.
PAGE 37
Figure 15.
PAGE 38
Figure 16.
PAGE 39
Figure 17.
PAGE 40
Figure 18.
PAGE 41
CDB42448 Figure 19. Silk Screen 9.
PAGE 42
Figure 20.
PAGE 43
Figure 21.
PAGE 44
CDB42448 10. REVISION HISTORY Revision Date Changes DB1 July 2004 Initial Release DB2 OCT 2004 Removed Bill of Materials Layer Changes: Corrected silk screen lables for S1, J8, J11 on Figure 19 on page 41. Changed bottom layer lot number on Figure 21 on page 43. Table 11. Revision History Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IIMPORTANT NOTICE Cirrus Logic, Inc.