Manual

CDB42438
DS646DB2 29
8. CDB BLOCK DIAGRAM
CS42438
CS8416
S/PDIF
Input
y Differential to
Single-Ended Output
y Single-Ended
Output
y Single-Ended to
Differential Input
y Single-Ended
Input
Serial Control Port
FPGA
CS8406
S/PDIF
Output
DSP HEADER
CS5341
Osc.
ANALOG INPUT
ANALOG OUTPUT
y Single-Ended
Input
AUXILIARY
ANALOG INPUT
MCLK Divided
Clocks
/Data
Hardware
Setup
MCLK BUS
Clocks & Data
Clocks/
Data
Clocks/Data
I
2
C/SPI Header
Power
Hardware
Control
Figure 7. Block Diagram
Figure 8 on page
30
Figure 12 on page 34 to
Figure 13 on page 35
Figure 10 on page
32
Figure 11 on page
33
Figure 9 on page 31
Figure 20 on page
42
Figure 14 on page 36 to Figure 15 on page 37
Figure 25 on page 47
Figure 16 on page 38 to
Figure 19 on page 41
Figure 21 on page 43 to
Figure 24 on page 46
Figure 20 on page 42