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Cirrus Logic, Inc.

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CDB42438

Evaluation Board For CS42438

Features

z Single-ended/Single-ended to Differential

Analog Inputs

z Single-ended/Differential to Single-ended

Analog Outputs

z CS8406 S/PDIF Digital Audio Transmitter

z CS8416 S/PDIF Digital Audio Receiver

z Header for Optional External Software

Configuration of CS42438

z Header for External DSP Serial Audio I/O

z 3.3 V Logic Interface

z Pre-defined Software Scripts

z S/PDIF-to-TDM Conversion for Easy

Evaluation of the TDM Digital Interface

z Demonstrates Recommended Layout and

Grounding Arrangements

z Windows

Compatible Software Interface to

Configure CS42438 and Inter-board

Connections

ORDERING INFORMATION

CDB42438 Evaluation Board

Description

The CDB42438 evaluation board is an excellent means

for evaluating the CS42438 CODEC. Evaluation re-

quires an analog/digital signal source and analyzer, and

power supplies. Optionally, a Windows

PC compatible

computer may be used to evaluate the CS42438 in soft-

ware mode.

System timing can be provided by the CS8416, or by a

DSP I/O stake header with a DSP connected. System

timing for TDM mode is provided by an FPGA using

clocks derived from the CS8416 or DSP I/O header.

RCA phono jacks are provided for the CS42438 analog

inputs and outputs. Digital data I/O is available via RCA

phono or optical connectors to the CS8416 and CS8406.

6 pre-defined board setup options are selectable using a

6-position DIP switch.

The Windows

software provides a GUI to make config-

uration of the CDB42438 easy. The software

communicates through the PC’s serial port to configure

the control port registers so that all features of the

CS42438 can be evaluated. The evaluation board may

also be configured to accept external timing and data

signals for operation in a user application during system

development.

CS42438

CS8416

S/PDIF

Input

y Differential to

Single-Ended

Output

y Single-Ended

Output

y Single-Ended to

Differential Input

y Single-Ended

Input

Serial Control Port

FPGA

CS8406

S/PDIF

Output

DSP HEADER

CS5341

Osc.

ANALOG INPUT

ANALOG OUTPUT

y Single-Ended

Input

AUXILIARY

ANALOG INPUT

MCLK Divided

Clocks

/Data

Hardware

Setup

MCLK BUS

ADC/DAC Clocks & Data

ADC/DAC

Clocks/

Data

Clocks/Data

C/SPI HeaderH/W Switches

OCT ‘04

DS646DB2

Summary of content (51 pages)

PAGE 1
CDB42438 Evaluation Board For CS42438 Features Description z Single-ended/Single-ended to Differential The CDB42438 evaluation board is an excellent means for evaluating the CS42438 CODEC. Evaluation requires an analog/digital signal source and analyzer, and power supplies. Optionally, a Windows® PC compatible computer may be used to evaluate the CS42438 in software mode.
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CDB42438 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................... 4 1.1 Power ................................................................................................................................. 4 1.2 Grounding and Power Supply Decoupling ......................................................................... 4 1.3 FPGA ...................................................................................
PAGE 3
CDB42438 LIST OF FIGURES Figure 1. Advanced Register Tab - CS42438 ................................................................................. 7 Figure 2. Advanced Register Tab - FPGA ...................................................................................... 8 Figure 3. Internal Sub-Clock Routing ............................................................................................ 10 Figure 4. Internal Data Routing ....................................................................
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CDB42438 1. SYSTEM OVERVIEW The CDB42438 evaluation board is an excellent means for evaluating the CS42438 CODEC. Analog and digital audio signal interfaces are provided, an FPGA used for easily configuring the board and a 9-pin serial cable for use with the supplied Windows® configuration software. The CDB42438 schematic set has been partitioned into 18 pages and is shown in Figures 8 through 25. 1.1 Power Power must be supplied to the evaluation board through the +5.0 V, +12.0 V and -12.
PAGE 5
CDB42438 clock on the OMCK input pin, and can operate in either the Left-Justified or I²S interface format. Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of the Cirrus Logic FlexGUI software. Refer to register “CS8406 Control (address 04h)” on page 17 for configuration settings. 1.
PAGE 6
CDB42438 Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of the Cirrus Logic FlexGUI software. Refer to register “DSP Header Control (address 07h)” on page 20 for configuration settings The 12-pin, 3 row header, J11, allows the user bidirectional access to the SPI/I2C control signals by simply removing all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable to the “EXTERNAL” position.
PAGE 7
CDB42438 2. SOFTWARE MODE The CDB42438 is shipped with a Microsoft Windows® based GUI, which allows control over the CS42438 and FPGA registers. Interface to the GUI is provided using an RS-232 serial cable. Once the appropriate cable is connected between the CDB42438 and the host PC, load “FlexLoader.exe” from the CDB42438 directory. Once loaded, all registers are set to their default reset state.
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CDB42438 Figure 2.
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CDB42438 3. FPGA SYSTEM OVERVIEW The FPGA (U16) controls all digital signal routing between the CS42438, CS8406 CS8416, CS5341 and the DSP I/O Header. For easy evaluation of the TDM interface format of the CS42438, the FPGA will copy stereo PCM data from either the CS8416 or DSP I/O Header onto one data line at a 256Fs data rate. It will in turn de-multiplex the TDM data from the CS42438 and output stereo channel pairs to the CS8406. 3.1 FPGA Setup Sections 3.2 to 3.
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CDB42438 3.2. Internal Sub-Clock Routing The graphical description below shows the internal clock routing topology between the CS42438, CS8416, CS8406 and DSP Header. Refer to registers “CODEC Clock Control (address 03h)” on page 17, “CS8406 Control (address 04h)” on page 17 and “CS8416 Control (address 05h)” on page 18 for configuration settings. CS8416 LRCK M/S CS8416 LRCK AUX LRCK CS42438 SCLK CS8416 SCLK CODEC_CLK.MUX[1:0] AUX SCLK DSP_FS FPGA->CODEC FS FS CODEC_CLK.
PAGE 11
CDB42438 3.3. Internal Data Routing The graphical description below shows the internal data routing topology between the CS42438, CS8416, CS8406 and DSP Header. Refer to registers “CODEC SDIN Control (address 02h)” on page 16, “CS8406 Control (address 04h)” on page 17 and “DSP Header Control (address 07h)” on page 20 for configuration settings.
PAGE 12
CDB42438 3.4. Internal TDM Conversion, MUXing and Control (TDMer) The graphical description below shows the routing topology of the TDM converter between the CS42438, CS8416, CS8406 and DSP Header. Refer to register “TDM Conversion (address 01h)” on page 16 for configuration settings. The TDMer allows the user to easily evaluate the CS42438 in the TDM digital interface format. A 256Fs clock and an FS pulse is derived from either the CS8416 or DSP Header.
PAGE 13
CDB42438 3.5 External MCLK Control Several sources for MCLK exist on the CDB42438. The crystal oscillator, Y1, will master the MCLK bus when no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for details on OMCK operation). This signal will be driven directly out the CS8416. The CS8416 will generate a master clock whenever its internal PLL is locked to the incoming S/PDIF stream.
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CDB42438 3.6 Bypass Control - Advanced The DSP clocks and data may be routed through buffers directly to the CS42438, bypassing the FPGA. This configuration may be desired for more stringent timing requirements at higher clock speeds. See register “Bypass Control (address 06h)” on page 19. These bits are only accessible through the Advanced tab of the Cirrus Logic FlexGui software. Setting “Bypass_FPGA” to ‘0’b will route the DSP sub-clocks directly to the CODEC.
PAGE 15
CDB42438 4. FPGA REGISTER QUICK REFERENCE Function 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved PDN_TDMer 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved SDIN.MUX1 SDIN.
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CDB42438 5. FPGA REGISTER DESCRIPTION All registers are read/write. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. 5.1 TDM CONVERSION (ADDRESS 01H) 7 6 5 4 3 2 1 0 DSP/CS8416 Reserved Reserved Reserved Reserved Reserved Reserved PDN_TDMer 5.1.
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CDB42438 5.3 CODEC CLOCK CONTROL (ADDRESS 03H) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved CLK_MUX1 CLK_MUX0 FPGA->CODEC 5.3.1 MUX (CLK_MUX) Default = 11 CLK_MUX[1:0] 00 01 10 11 Clock Selection Reserved Reserved DSP TDMer Table 2. Clocks toCODEC Function: This MUX selects the sub-clock lines from the DSP Header and the sub-clocks from the TDMer internal to the FPGA (see Figure 3 on page 10). 5.3.
PAGE 18
CDB42438 Function: This MUX selects the data lines from the ADC’s and the external ADC. The last 4 selections are demultiplexed from the TDM stream of SDOUT (see Figure 5 on page 12). 5.4.2 OMCK/LRCK RATIO SELECT (OMCK 128/256 FS) Default = 0 0 - 256 Fs 1 - 128 Fs Function: Selects the MCLK/LRCK ratio of the CS8406 transmitter. 5.4.3 LEFT-JUSTIFIED OR I²S INTERFACE FORMAT (I²S/LJ) Default = 0 0 - Left Justified 1 - I²S Function: Selects either I²S or Left Justified interface format for the CS8406. 5.
PAGE 19
CDB42438 is held low for 300 µs whenever this bit changes. 5.5.3 RMCK/LRCK RATIO SELECT (128/256 FS) Default = 0 0 - 256 Fs 1 - 128 Fs Function: Selects the RMCK/LRCK ratio for the CS8416. Pin 6 (RST bit) is held low for 300 µs whenever this bit changes. 5.5.4 LEFT-JUSTIFIED OR I²S INTERFACE FORMAT (I²S/LJ) Default = 0 0 - Left-Justified 1 - I²S Function: Selects either I²S or Left Justified interface format for the CS8416. Pin 6 (RST bit) is held low for 300 µs whenever this bit changes. 5.5.
PAGE 20
CDB42438 5.6.2 DSP DATA ROUTE TO DAC (DSPDATA->DAC) Default = 1 0 - Enable 1 - Disable Function: This bit toggles a control line for the data buffer external to the FPGA to route the DSP Data directly to the DAC. The inverted signal controls active low buffers internal to the FPGA that routes the FPGA data to the DAC. Refer to Figure 4 on page 11. 5.6.
PAGE 21
CDB42438 5.7.2 DSP MCLK (MCLK_M/S) Default = 0 0 - DSP MCLK is a slave to the MCLK bus. 1 - DSP MCLK masters MCLK bus. Function: Enables/disables the external DSP MCLK output buffer on the MCLK bus.
PAGE 22
CDB42438 5.8 CS5341 AND MISCELLANEOUS CONTROL (ADDRESS 08H) 7 6 5 4 3 2 1 0 Reserved Reserved INT.MCLK_ DIV INT.DIV_ 1.5/2 ‘41_MCLK_ DIV ‘41_DIV_ 1.5/2 ‘41_I²S/LJ ‘41_RST 5.8.1 INT MCLK DIVIDE (1.5/2.0 DIVIDE) Default = 0 0 - Disabled 1 - Enabled Function: Enables/disables the internal (1.5 or 2.0) divide circuitry for MCLK. 5.8.2 1.5 OR 2.0 MCLK DIVIDE (1.5/2.0 DIVIDE) Default = 0 0 - Divide by 1.5 1 - Divide by 2.0 Function: Divides the internal MCLK by 1.5 or 2 to all internal logic.
PAGE 23
CDB42438 Function: Selects either I²S or Left Justified interface format for the CS5341. Reset to the CS5341 is toggled. 5.8.6 RESET (‘41_RST) Default = 1 0 - CS5341 is held in reset 1 - CS5341 is taken out of reset Function: This bit toggles pin 30 of the FPGA and is held low for 300 µs upon FPGA initialization. It will also be held low for 300 µs whenever register 08h[1] changes.
PAGE 24
CDB42438 6. HARDWARE MODE Switch S1 configures the CDB42438 in hardware mode. Switch S5 sets up the FPGA and controls the routing of all clocks and data. Refer to section 6.1 for a list of the various hardware mode options available. After setting any of these switches, the user may need to assert a reset by pressing the “RESET” button (S4) or the “PROGRAM” button (S2) . 6.1 Setup Options The setup options below allow the user to configure the CDB42438 when the CS42438 is in hardware mode.
PAGE 25
CDB42438 3 SW[3:0] General Description 0011 TDMer w/CS8416 Data (S/PDIF4) 1) CS8416 Masters MCLK & PCM Subclocks 2) CS8416 data duplicated and Time-Division Multiplexed into DAC_SDIN. 3) External ADC (AUX1-2) de-multiplexed from ADC_SDOUT and input into CS8406. Register Address Value Detail Description 01h 00h TDM Conversion - CS8416 clocks & data to TDMer. 02h 03h SDIN Control - TDMer output data input to SDIN. 03h 36h CODEC Clock Control - CODEC slave to TDMer.
PAGE 26
CDB42438 15 26 SW[3:0] General Description 1111 TDMer w/Digital Loopback 1) Oscillator Y1 Masters MCLK passed through CS8416. [REMOVE S/PDIF INPUT] 2) ADC SDOUT into DAC SDIN. Register Address Value Detail Description 01h 00h TDM Conversion - CS8416 clocks & data to TDMer. 02h FEh SDIN Control - ADC_SDOUT input to DAC_SDIN. 03h 36h CODEC Clock Control - CODEC slave to TDMer.
PAGE 27
CDB42438 7. CDB CONNECTORS AND JUMPERS CONNECTOR Reference Designator INPUT/OUTPUT SIGNAL PRESENT +5V J2 Input +5.0 V Power Supply +12V J5 Input +12.0 V Power Supply -12V J4 Input -12.
PAGE 28
CDB42438 JUMPER PURPOSE POSITION FUNCTION SELECTED J1 Selects source of voltage for the VA supply +3.3V *+5V AIN1(J26) Selects the negative leg of the single-ended to differential input circuit in differential mode, or a VA/2 bias in single-ended mode. *DIFF IN SINGLE IN Inverted signal from AIN1 input VA/2 voltage bias AIN2(J22) Selects the negative leg of the single-ended to differential input circuit in differential mode, or a VA/2 bias in single-ended mode.
PAGE 29
DS646DB2 Osc. Figure 9 on page 31 DSP HEADER Figure 13 on page 35 32 FPGA Figure 12 on page 34 to Clocks /Data Hardware Setup MCLK BUS Clocks/ Data Hardware Control Figure 10 on page CS8416 S/PDIF Input 33 Figure 11 on page CS8406 S/PDIF Output Clocks/Data Clocks & Data 42 Figure 20 on page CS5341 Figure 7.
PAGE 30
CDB42438 Figure 8. CS42438 9.
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Figure 9.
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Figure 10.
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Figure 11.
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Figure 12.
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Figure 13.
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Figure 14.
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Figure 15.
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Figure 16.
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Figure 17.
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Figure 18.
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Figure 19.
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Figure 20.
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Figure 21.
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Figure 22.
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Figure 23.
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Figure 24.
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Figure 25.
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CDB42438 Figure 26. Silk Screen 10.
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Figure 27.
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Figure 28.
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CDB42438 11. REVISION HISTORY Revision Date Changes DB1 July 2004 Initial Release DB2 OCT 2004 Removed Bill of Materials Schematic Changes: Changed R224, R226, R228, R230, R234, R235, R236, R237 from 6.19 kΩ to 4.75 kΩ on Figure 21 on page 43, Figure 22 on page 44, Figure 23 on page 45, Figure 24 on page 46. Layer Changes: Corrected silk screen lables for S1, J8, J11, and J24 on Figure 26 on page 48. Changed bottom layer lot number on Figure 28 on page 50. Table 7.