AN83 Application Note &U\VWDO /$1 CS8900A ETHERNET CONTROLLER TECHNICAL REFERENCE MANUAL By Deva Bodas Revised by James Ayres Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Copyright Cirrus Logic, Inc.
AN83 TABLE OF CONTENTS SCHEMATIC CHECKLIST ...................................................................................................................................4 SOFTWARE CHECKLIST ....................................................................................................................................5 INTRODUCTION TO CS8900A TECHNICAL REFERENCE MANUAL ..............................................................6 HARDWARE DESIGN ....................................................
AN83 LOW COST ETHERNET COMBO CARD REFERENCE DESIGN: CRD8900 .................................................. 21 General Description ............................................................................................................................... 21 Board Design ......................................................................................................................................... 21 Crystal Oscillator ..........................................................................
AN83 Good to have pads, don’t populate except for EMI problems. SCHEMATIC CHECKLIST Before getting into the meat of the technical reference manual here is a schematic checklist. It’s presented here, at the beginning, to help the hardware designer implement the design quickly and easily. 4 - Isolation transformer -- start with one that does not have a common mode choke. If there are EMI considerations, then use one with common mode choke. The pin outs are the same. For 3.
AN83 SOFTWARE CHECKLIST - - - When servicing the interrupt always read the Interrupt Status Queue (ISQ) first. Process that individual event before reading the ISQ again. Having read an ISQ event indicating a valid recieve frame, never read the ISQ again before either 1) reading in the entire current receive frame or 2) issuing an explicit skip command. Either of these actions will correctly clear that frame from the CS8900A’s internal memory.
AN83 INTRODUCTION TO CS8900A TECHNICAL REFERENCE MANUAL This Technical Reference Manual provides the information which will be helpful in designing a board using the CS8900A, programming the associated EEPROM, and installing and running the CS8900A device drivers. It is expected that the user of this technical reference manual will have a general knowledge of hardware design, Ethernet, the ISA bus, and networking software.
AN83 gram and read the CS8900A control and status registers, and how to transfer user data between the CS8900A and the PC main memory via the ISA bus. On the NOS side, the drivers provide the standardized services and functions required by the NOS, and hide all details of the CS8900A hardware from the NOS. The EEPROM device programs the CS8900A whenever the a hardware reset occurs, and call also store state/configuration information for the driver.
AN83 ISA Bus An ISA bus is a simple, asynchronous bus that can easily be made to interface to most synchronous or asynchronous buses. An ISA bus has separate address and data lines as well as separate control lines for read and write. ISA supports IO address space of 64K bytes and Memory address space 32 Mega bytes. CS8900A in I/O Mode When the CS8900A is used in an IO mode, it responds in the IO address space of the ISA.
AN83 long as the CS8900A contains frames completely received. If ‘n’ words are to be transferred from the CS8900A to the system RAM, the DRQ signal remains active until the (n-1)th word is transferred. If the DMABurst is set, then the CS8900A deasserts DRQ signal for 1.3 µs after every 28 µs. This option is provided so that in a system where multiple DMA channels are operational, the DMA used for the CS8900A will not take over the system bus for long periods of time.
AN83 When the MC68302 generates address 0D00300h, the address seen by the CS8900A will be 00300h with one of the IO commands (IOR or IOW) active. Similarly when the MC68302 generates address 0D01400h, the address seen by the CS8900A will be 01400h with one of its memory commands (MEMR or MEMW) active. For a MC68302, you can also specify the number of wait states that should be inserted automatically when address space assigned to CS1 is accessed.
AN83 Status Signals from CS8900A There are several status signals that are output from the CS8900A, such as IOCHRDY, IOCS16, MCS16, etc. In the most embedded designs, they are not needed. Those pins from the CS8900A should be left open. Databus (SD[0:15]) Connection All the internal registers of the CS8900A are 16 bit wide. For all the registers, bit F of the register is access via SD15 and bit 0 of register is accessed via SD0.
AN83 in BIOS. If the designer intends to use Cirrus supplied drivers and does not use an EEPROM or store driver configuration data in BIOS, then Cirrus supplied drivers must be modified by the designer. We recommend that the system store the individual IEEE MAC address in a non-volatile memory somewhere in the system, and that the end-user of the system not be allowed to create an arbitrary address.
AN83 R96 4K99 1% VDD VDD GND VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 R97 100K GND nMWE nMOE nCS2 nMWE nMOE nCS2 CS8900_RST GND SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 65 66 67 68 71 72 73 74 27 26 25 24 21 20 19 18 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 7 28 29 62 61 49 36 63 75 77 76 2 CHIPSEL MEMW MEMR IOW IOR REFRESH SBHE AEN RESET SLEEP TESTSEL ELCS 97 98 XTLI XTLO X3 AVDD1 AVDD2 AVDD3 R
AN83 0.1uF 1 70 AVSS0 69 DVDD4 96 AVSS4 AVDD3 95 0.1uF 94 AVSS3 0.1uF 86 85 AVDD2 AVDD1 AVSS2 0.1uF 90 89 AVSS1 57 DVSS3A DVDD3 56 0.1uF 55 DVSS3 22 23 DVSS2 DVDD2 9 10 DVSS1A DVSS4 DODO+ 84 83 DIDI+ 80 79 CICI+ 82 81 RXDRXD+ TXDTXD+ 92 91 88 87 BSTATUS/HC1 LINKLED/HC0 LANLED CSOUT RDX100 RXD+ TXD- 8 560pF TXD+ 8 78 99 100 17 LED 3.
AN83 ETHERNET HARDWARE DESIGN FOR EMBEDDED SYSTEMS AND MOTHERBOARDS the CS8900A to interface with variety of microprocessors directly or with the help of simple programmable logic like a PAL or a GAL. This section describes the hardware design of a four-layer, 10BASE-T solution intended for use on PC motherboards, or in other embedded applications. The goal of this design is minimal board space and minimal material cost.
C S 890 0 E V A L R E V . B C D B 8900B © C O P Y R IG H T 1994 CRYSTAL SEM IC OND UCTOR CO RPO RATIO N CS8900 EVAL BOARD REV. B P/N CDB8900B AN83 Figure 6.
CRYSTAL SEMICONDUCTOR CO RPORATION CS8900 EVAL BOARD REV. C P/N CDB8900B AN83 Figure 7.
AN83 PROM is not necessary for the CS8900A, and the CS8900A will respond to IO addresses 0300h through 030Fh after a reset. Please refer to the CS8900A data sheet for information about programming the EEPROM. Please refer to “JUMPERLESS DESIGN” on page 45 of this document for information about EEPROM internal word assignments. LEDs Many embedded systems do not require LEDs for the Ethernet traffic. Therefore this reference design does not implement any LEDs.
AN83 C12 C14 C13 C9 C8 C11 C10 0.1µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F +5V +5V 0.
AN83 1 10BT_RD100 R2 10BT_RD+ 10BT_TD24.3 R4 68 pF C30 10BT_TD+ 24.3 R5 16 16 15 15 2 2 3 3 4 4 13 13 5 5 12 12 6 6 (1-3) (16-14) 1:1 10 8 7 6 5 4 3 2 1 14 14 11 11 (6-8) (11-9) 1:1.414 7 7 10 10 8 8 9 9 J1 9 10 BaseT Transformer Do Not Populate .1 µF Do Not Populate .1 µF 2KV C29 .1 µF C23 .1 µF 2KV C28 Figure 10.
AN83 LOW COST ETHERNET COMBO CARD REFERENCE DESIGN: CRD8900 This section describes the hardware design of a lowcost, two-layer, full-featured Ethernet solution intended for use in PC ISA-bus. The goal of this design is a high degree of application flexibility. Therefore, a number of features (BootPROM, AUI, 10BASE-2) are supported. An example of this circuit is included in this Technical Reference Manual.
U6 + C1 C4 U6 U7 C3 U4 C2 U3 C S 8900 C O M B O E V A L R E V . B C D B 8900B © C O P Y R IG H T 1994 C 10 X1 C8 R2 R4 R5 C30 + C11 R3 C12 C 13 U1 C6 C9 1 C7 C5 C17 C16 R6 C14 R7 R8 C15 R9 U5 C 18 C 1P CRYSTAL SEM ICONDUCTOR CORPORATIO N CS8900 COMBO EVAL BO ARD REV. B P/N CDB8900B + R10 U2 C20 T1 C21 T3 C28 U9 R 16 D1 R 15 J1 J3 R 17 C27 R 11 R 12 R 13 R 14 C 24 C23 C29 C26 F1 T2 C22 LE D 1 T B J2 R 19 R 18 J4 AN83 Figure 12.
AN83 C8 C7 C11 C13 C12 0.1µ F 0.1µ F 0.1µ F 0.1µ F 0.1µF EE_DIN C17 0.1µ F EE_CLK C16 0.1µ F +5V +5V 0.
AN83 +5V C19 + C10 TANT TANT 22µ F 22µ F + C1 TANT 22µ F + GND Figure 14. Power Supply Decoupling Schematic PROM_CS C2 20 22 1 SA00 SA01 SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SA10 SA11 SA12 SA13 SA14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 +5V 0.1µ F C4 CE OE VPP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 0.1µ F 4.
AN83 F1 +12V R6 39.2 C14 0.1µ F R7 39.2 CON_AUI15PSUBO DODO+ DIDI+ 1 2 4 5 7 8 CICI+ DIDI+ 39.2Ω R9 CICI+ R8 VP_+12V 39.2 T2 I11 I12 I21 I22 I31 I32 CI_A DO_A O11 16 O12 15 O21 13 O22 12 O31 10 O32 9 1 2 3 9 CI_B 10 DO_B 4 DI_A 11 J2 12 5 13 6 AUI_XFR_S 14 7 C15 0.1µ F DI_B 15 8 16 C27 17 0.1µ F Figure 16. AUI Schematic 1 +12V BSTATUS/HCI C18 0.1µ F 2 3 22 23 24 +12IN1 12 SOUT+ +12IN2 SOUT- 9 EN U5 EN -12IN1 -12IN2 ISOLATED_GND C21 0.1µ F C20 0.
AN83 loaded at the Boot PROM base address register indicates the starting location in host memory where the Boot PROM is mapped. The Boot PROM address mask indicates the size of the Boot PROM. The lower 12 bits of the mask are ignored and should be 000h. This limits the 434 Boot PROM size to increments of 4K bytes. The CS8900A will not generate an address decode for the Boot PROM until the Boot PROM base address register and the mask register are loaded.
AN83 10BASE-2 Interface A 10BASE-2 transceiver IC, the 83C92C, is used to generate a 10BASE-2 interface for the reference design. Please refer to Figure 17 for details about the components and connection. A 12 volt to -9 volt DC to DC voltage converter (location U5) is used to generate an isolated -9 volt supply for the 83C92C. The DC-DC converter used in the reference design has an enable pin. This enable pin is connected to the HC1 pin of the CS8900A.
AN83 Figure 19.
AN83 Figure 20.
AN83 Item Reference # Description Quantity Vendor Base Configuration: I/O Mode with 10BASE-T Interface 1 C5, C7, C8, Capacitor, 0.1 µF, SMT0805, X7R 11 C11..13, C16, C17, C22, C23, C27 2 C1, C10, C19 Capacitor, 22 µF, SMT7343 3 3 R3 Resistor, 4.99K, 1%, SMT0805 1 4 R18, R19 Resistor, 681, 5%, 1/8W, SMT0805 2 5 X1 Crystal, 20.000MHz,18 pF 1 M-tron 6 J4 Board Bracket 1 Globe 7 U1 ISA Ethernet Controller 1 Crystal 8 U3 1K EEPROM 1 Microchip 9 R4, R5 Resistor, 24.
AN83 Memory Mode Extended Memory Mode In the memory mode, there are two options where the CS8900A can be placed in the ISA memory address map, lower memory (below 1 Meg) or extended memory (above 1 Meg). The lower memory typically consists of the conventional memory (up to 640K) and upper memory (640K to 1 Meg. boundary). To access anything in extended memory, the processor (386 and above) is used in the “Enhanced Mode”.
AN83 Connector Isolation Transformer or Transformer with CMC Terminating Resistors Ethernet Interface AUI or 10 BASE-T CS8900 Figure 22. Typical CS8900A Ethernet Connection face is used to generate the serial data stream on EEDataOut pin (serial data out) with the EESK (serial clock). Whenever ELSEL bit is set, ELCS pin becomes active (LOW) instead of EECS pin during the EEPROM operations. Since the EECS pin remains inactive, the EEPROM that is interfaced to the CS8900A is not enabled.
AN83 Figure 23 shows a simple PALASMTM program for the 16R4 PAL that is used in the design shown in Figure 21.
AN83 Q20 := (Q20 * CS_EL_b) + (/CS_EL_b * SDATA) Q21 := (Q21 * CS_EL_b) + (/CS_EL_b * Q20) Q22 := (Q22 * CS_EL_b) + (/CS_EL_b * Q21) Q23 := (Q23 * CS_EL_b) + (/CS_EL_b * Q22) ; Decode logic EQUALL = (Q20:*:LA20) * (Q21:*:LA21) EQUALH = (Q22:*:LA22) * (Q23:*:LA23) ADD_VALID = /RESET * CS_EL_b * ADD_VALID ; :*: -> Exclusive NOR operator ; stay clear till any write + /RESET * /CS_EL_b ; Set when address write + /RESET * ADD_VALID ; Remain set until reset CHIPSEL_b = RESET ; Get set at RESET
AN83 Layout Considerations for the CS8900A The CS8900A is a mixed signal device having digital and analog circuits for an Ethernet communication. While doing the PCB layout and signal connections, it is important to take the following precautions: - Provide a low inductive path to reduce power and ground connection noise. - Provide proper impedance matching especially to the Ethernet analog signals. - Provide low inductive path, wider and short traces, for all analog signals.
U6 + C1 C4 U6 U7 C3 U4 C2 U3 C S 8900 C O M B O E V A L R E V . B C D B 8900B © C O P Y R IG H T 1994 C 10 X1 C8 R2 R4 R5 C30 + C11 R3 C12 C 13 U1 C6 C9 1 C7 C5 C17 C16 R6 C14 R7 R8 C15 R9 U5 C 18 C 1P CRYSTAL SEM ICONDUCTOR CORPORATIO N CS8900 COMBO EVAL BO ARD REV. B P/N CDB8900B + R10 U2 C20 T1 C21 T3 C28 U9 R 16 D1 R 15 J1 J3 R 17 C27 R 11 R 12 R 13 R 14 C 24 C23 C29 C26 F1 T2 C22 LE D 1 T B J2 R 19 R 18 J4 AN83 Figure 24.
AN83REV3 C S 8900 E V A L R E V . B C D B 8900B © C O P Y R IG H T 1994 CRYSTAL SEM ICONDUCTO R CO RPO RATIO N CS8900 EVAL BO ARD REV. B P/N CDB8900B AN83 Figure 25.
CRYSTAL SEM ICONDUCTOR CO RPO RATION CS8900 EVAL BOA RD REV. C P/N CD B8900B AN83 Figure 26.
AN83 Figure 27. Component (top) side of four-layer board Figure 2.4.6.
AN83 Figure 28. +5V Plane of four-layer board Figure 2.4.7.
AN83 Figure 29. Ground Plane of four-layer board Figure 2.4.8.
AN83 Figure 30. Solder side (bottom) of four-layer board Figure 2.4.9.
AN83 Figure 31. Placement of Decoupling Capacitor (Bottom side, under CS8900A) Figure 32. Routing of Decoupling Capacitor (Top side, component side) The 20.000 MHz crystal traces should be short, have no via, and run on the component side. Biasing resistor at RES pin of the CS8900A: A 4.99 KΩ resistor is connected between pins RES (pin #93) and AVSS3 (pin #94) of the CS8900A.
AN83 mit signal traces should be at least 100 mil. This will provide a good impedance matching for the transmit and receive circuitry inside the CS8900A. A ground trace should be run parallel to the transmit traces. Also, a ground plane should run underneath the transmit and receive traces on the solder side of a two layered PCB. Please refer to the Figures 33 and 34 for illustration of the above guide lines.
AN83 able in a 16 pin DIP or 16 pin SOIC package. See tables 4 and 5 for recommended part numbers. JUMPERLESS DESIGN Using the CS8900A, both add-in adapters and motherboard solutions can be implemented without hardware jumpers or switches. The CS8900A and media access control (MAC) device drivers obtain configuration information directly from nonvolatile memory. For add-in ISA adapters, a serial EEPROM will be connected directly to the CS8900A via the serial interface.
AN83 Vendor name Halo Electronics Pulse Engineering Valor Electronics Description Isolation transformer, 100 µH Isolation transformer, 100 µH Isolation transformer, 100 µH Through-hole TD01-1006K PE-64503 LT6033 Surface-mount TG01-1006N PE-65728 ST7033 Table 4. Partial List of Recommended AUI Transformers Vendor name Halo Electronics Pulse Engineering Valor Electronics Description Transformer 1:1::1:1.41 Transformer with CMC Industrial temperature 1:1::1:1.41 Industrial temperature 1:1::1:1.
AN83 Sheet for additional information on the operation of the EEPROM. Addr 00h 01h 02h 03h 04h 05h 06h 07h 08h Word A110h 0020h 0210h 3030h 8000h 000Ch C000h 000Fh 1600h Description Sequential EEPROM, 16 bytes follow 1 word into PP_020 (IO Base Addr) IO Base Address = 210h 4 words beginning at PP_030 Boot PROM base at C8000h Typically, this additional configuration information includes the unique IEEE physical address for the adapter.
AN83 Addr. 23h 24h 24h Description Transmission Control HDX/FDX Reserved Ignore Missing Media Reserved Adapter Configuration Ext.
AN83 IEEE Physical Address The format of the 48-bit IEEE physical address as expected by the MAC driver is illustrated by the following example. (Must be initialized by OEM before shipping adapter.) Example physical address: 000102030405h Addr 1Ch 1Dh 1Eh Word Description 0100h 2 MSB of address (byte reversed) 0302h Middle 2 bytes (byte reversed) 0504h 2 LSB of address (byte reversed) ISA Configuration Flags The ISA Configuration Flags specify how the CS8900A will utilize ISA system resources.
AN83 PacketPage Memory Base Bits 15-4 12 MSB of Memory Base Address - The twelve most significant bits of the 24-bit address locating the base of the CS8900A’s PacketPage memory. The lower twelve bits are assumed to be 0. Default is 0. Bits 3-0 Reserved (set to 0) Boot PROM Memory Base Bits 15-4 12 MSB of Memory Base Address - The twelve most significant bits of the 24-bit address locating the base of the CS8900A’s PacketPage memory. The lower twelve bits are assumed to be 0. Default is 0.
AN83 Adapter Configuration Word Bits 15-13 Reserved (set to 0) Bits 12-11 Optimization Flags Used to specify the platform’s OS configuration to the driver. Each driver configures the CS8900A for optimum performance based on the platform’s OS and driver architecture (NDIS 2X, ODI, NDIS 3X, etc.). Default is DOS (single threaded OS). Bits 10-8 Reserved (set to 0) Bit 7 DC to DC Converter Polarity Refer to “10BASE-2 Interface” on page 27. (Must be initialized by OEM before shipping adapter.
AN83 Manufacturing Date This word is the adapter’s manufacture date encoded in 16 bits, YR-MO-DY format. (Must be initialized by OEM before shipping adapter.) Bits 15-9 Two Least-significant Digits of Year Seven bits for a range of 00 to 99 decimal. A roll-over to 00 will be interpreted as the year 2000. Bits 8-5 Month Four bits for a range of 01 to 12. Bits 4-0 Day Five bits for a range of 01 to 31. IEEE Physical Address (Copy) This field is a copy of the three words at address 1Ch to 1Eh.
AN83 Serial Number The two serial number words make up the unique 32-bit OEM serial number for the adapter. Low Word Bits 7-0 bits[7-0] of 32-bit serial number Bits 15-8 bits[15-8] of 32-bit serial number High Word Bits 7-0 bits[31-24] of 32-bit serial number Bits 15-8 bits[23-16] of 32-bit serial number Serial ID Checksum Word 34h contains an 8-bit LFSR checksum calculated on the EISA ID and OEM serial number (words 30h to 33h). The 8-bit LFSR checksum is placed in the low byte of 34h.
AN83 Maintaining EEPROM Information The contents of the EEPROM may either be preprogrammed in a stand-alone EEPROM programmer or programmed after installation through the CS8900A’s serial interface. See the CS8900A Data Sheet for programming an EEPROM via the CS8900A’s serial interface. The OEM is left to determine the best procedure for programming EEPROMs via a stand-alone EEPROM programmer. Cirrus has two utilities suitable for maintaining the configuration information stored in the EEPROM. IAGEN.
AN83 ture storing the Driver Configuration Block in BIOS space.
AN83 DEVICE DRIVERS AND SETUP/INSTALLATION SOFTWARE This chapter discusses the software provided by Cirrus for use with the CS8900A. That software includes a broad family of device drivers, driver-related data files, and utilities. A single-user, evaluation copy of that software is included with this Kit. The following drivers are included in the Kit: - Novell ODI 4.x DOS (for use with Netware clients) - Novell ODI 4.x OS/2 driver (for use with Netware OS/2 clients) - Novell ODI 4.
AN83 4) The current configuration of the adapter will be displayed. Click on OK or press the Enter key to proceed. 5) Press the ALT key then use the Adapter/Manual configuration options to manually override any of the current configurations setting shown. 6) Use Diagnostics/Self Test to test the functionality of the card. We invite you to contact us for assistance at any time during the design process.
