AN379 Application Note Design Guide for a CS1680 Dimmable LED Driver IC for Low-voltage Lighting 1 Overview of the CS1680 The CS1680 is a cascade boost-buck dimmable LED driver for the 12V halogen lamp-replacement market. The CS1680 uses a Cirrus Logic proprietary intelligent digital control that provides exceptional single-lamp and multi-lamp transformer compatibility for non-dimmer systems and dimmer systems paired with electronic and magnetic low-voltage transformers.
AN379 IMPORTANT SAFETY INSTRUCTIONS Read and follow all safety instructions prior to using this demonstration board. This Engineering Evaluation Unit or Demonstration Board must only be used for assessing IC performance in a laboratory setting. This product is not intended for any other use or incorporation into products for sale. This product must only be used by qualified technicians or professionals who are trained in the safety procedures associated with the use of demonstration boards.
AN379 2 Introduction This application note is a guide to designing a low-voltage solid-state lighting (SSL) LED lamp circuit using Cirrus Logic's CS1680. The first half of the design guide presents a step-by-step design procedure for calculating the required components for each stage of the system. The second half of the design guide uses a Cirrus Logic CRD1680-7W reference design as an example to verify the design procedure.
AN379 2.
AN379 3 Design Process The design process for a two-stage power converter system can be partitioned into five circuit blocks (see Figure 1). The AC line voltage is rectified, then converted to the desired DC output by a boost converter. The power converter system includes the startup circuit, steady state supply, and active clamp support circuitry.
AN379 3.1 Operating Parameters To initiate the design procedure, a set of operating parameters is required. Operating parameters required for the analytical process are outlined in the table below. Parameters Symbol POUT Output Power VIN AC Input Voltage Output Voltage VOUT Load Current IOUT Maximum Buck Switching Frequency* FBUCKSW(max) * Increasing the switching frequency may reduce the size of the magnetics but increase switching losses in the FET and transformer.
AN379 3.3 Buck Stage Design Figure 2 illustrates the steps for designing the buck stage. Buck Specification Steps for the Buck Design 1. Set the boost output voltage VBST. Determine VBST, VBreakdown, and VMargin 2. Determine the FET breakdown voltage VBreakdown and margin voltage VMargin. 3. Select a FET that aligns with the quality standards of the designer’s company. Define GAINTT and (T1BUCK + T2BUCK ) 4. Determine critical period (T1BUCK +T2BUCK ). 5. Define gain factor GAINTT.
AN379 The Buck Topology Figure 3 illustrates a typical implementation of a buck converter using the CS1680 controller. The load is composed of a string of LEDs. Diode DBUCK is the catch diode, also known as the freewheeling diode, and its function is to allow the current to flow in inductor LBUCK and to the load after FET QBUCK turns off.
AN379 The CS1680 maximum switching frequency is 312.5kHz. Test results indicate that optimal performance is obtained in the range of 75kHz to 225kHz. Higher frequencies allow the use of smaller magnetics, but switching losses increase. Selecting too low a full brightness switching frequency risks allowing the minimum frequency to drop into the audible range. Equation 1 defines the buck stage switching frequency TTBUCK(fb) at full brightness: 1 TT BUCK fb = -------------------------F BUCKSW [Eq.
AN379 Dimming Operation The dimmer conduction time or phase cut information is extracted by the boost stage and supplied to the buck stage as a digital parameter, dim, ranging from 0.05 to 1 as a measure of the normalized output power to be delivered. The dim parameter controls both the normalized peak current in the inductor and total period TTBUCK.
AN379 Step 2) Select an Appropriate FET Determine the FET breakdown voltage VBreakdown and margin voltage VMargin. The maximum FET drain voltage VDrain(max) is defined when power FET QBUCK is turned off and calculated using Equation 8: V Drain max = V BST BOP + V Diode [Eq. 8] where VDiode = forward voltage across catch diode DBUCK VBST(BOP) = boost output voltage at the boost overvoltage protection (BOP) threshold Voltages closely approaching the buck power FET breakdown voltage are acceptable.
AN379 Step 5) Calculate Buck Sense Resistor The CS1680 current sense threshold VBUCKPK(th) is set by the buck sense resistor. The voltage drop across sense resistor RBUCK(Sense) equals threshold VBUCKPK(th) at a maximum peak current IBUCKPK(max). Calculate resistor RBUCK(Sense) using Equation 14: V BUCKPK th R BUCK Sense = -------------------------------I BUCKPK [Eq.
AN379 Step 8) Buck Inductor Specification This step is the first iteration of the inductor design. Due to design constraints, the following requirements must be met: • The core must be big enough to fit the windings. • The number of turns required must fit in the bobbin, along with insulation material. • The finished inductor must not overheat in the environment. • Magnetic and geometric constraints may not yield the exact value of inductor LBUCK.
AN379 can be added to suppress high frequency ringing on the drain node. A resistor divider may be inserted at the BUCKZCD input to limit the input current and reduce the zero-crossing switching signal. 3.4 Boost Stage Design The boost stage is a low-side asynchronous boost converter. Once the CS1680 reaches its UVLO start threshold voltage VST(th) and begins normal operation, the controller executes an algorithm to set the operating state of the IC (see Table 1 on page 14).
AN379 power in poor dimmer/transformer combinations. The Mode3 algorithm requires maximum peak current IBSTPK(max) to be set by sense resistor RBST(Sense) and target power PTarget to be set by resistor RCTRL1. 3. The Mode2 algorithm requires a minimum average current to equal 1.6A during the turn-on time of the electronic transformer. The turn-on time of the transformer is estimated based on the output power requirement for the particular conduction angle by the regulation loop.
AN379 Step 12) Calculate Boost Sense Resistor Maximum peak current IBSTPK(max) is set by the boost sense resistor. Boost sense resistor RBST(Sense) is designed to hit peak current IBSTPK(max) at threshold voltage VBSTPK(th). Once peak current IBSTPK(max) is derived from Equation 25, calculate sense resistor RBST(Sense) using Equation 26: V BSTPK th R BST Sense = -------------------------------I BSTPK max [Eq.
AN379 the CCM algorithm. Boost inductance LBST does not affect the switching frequency. Changes to the boost inductor alters only the peak-to-peak ripple of the boost current. The boost inductor design should support a ripple current at maximum boost output voltage VBST(max) and when the instantaneous rectified input voltage applied to the boost stage inductor is at a 30 conduction angle.
AN379 Step 17) Boost Input Capacitor Selection To sustain compatibility with a wide range of transformers paired with a leading-edge or trailing-edge dimmer, the boost input capacitance should be minimized. Large input capacitance impacts the ability of the controller to properly sustain the current required by a transformer paired with a dimmer and may cause oscillation. Capacitors should not be connected to the AC line side of a bridge rectifier.
AN379 resistor RCLAMP must comply with the relation defined in Equation 38: 2 2 0.022 V CLAMP V BST full K CLAMP on R CLAMP ------------------------------------------- = ---------------------------------------------------------------------45.5 P OUT min P OUT min [Eq. 38] Using the denominators of Equations 37 and 38, the inequality PTarget ≥ 45.5 POUT(min) can be used to determine which function will determine the sizing of clamp resistor RCLAMP.
AN379 Step 22) Layout Basics for any power layout: 20 • Keep power traces as short as possible. • Keep the controller away from power components and traces if possible. Keep sensitive traces (all sense inputs) away from high dv/dt traces such as FET drain and FET gate drive. • Decouple the capacitor directly at the VDD pin of the CS1680 to GND.
AN379 4 Design Example The required operating parameters for the analytical process are outlined in the table below. Parameters Symbol Value POUT 5.15W VIN 12 VAC 10% Output Voltage VOUT 12V 10% Load Current IOUT 430 mA FBUCKSW(max) 150 kHz Output Power AC Input Voltage Maximum Buck Switching Frequency* * Increasing the switching frequency may reduce the size of the magnetics but increase switching losses in the FET and inductor. Notes: 1.
AN379 It is desirable to maintain a minimum margin of 8V and to use a FET with a breakdown voltage of 50V. Solving Equation 44 for voltage VMargin yields Equation 45: V M arg in = V Breakdown – 38V = 50V – 38V = 12V [Eq. 45] Step 3) Determine the Buck Stage Timing The buck stage operates in DCM at all times. Gain factor GAINTT is defined as constant equal to 1.2. Solving Equation 11 on page 11 for critical period (T1BUCK+T2BUCK) yields Equations 46: TT BUCK fb 6.
AN379 Calculate buck inductance LBUCK at maximum boost voltage VBST(max) and maximum voltage VOUT(max). The current through inductor LBUCK must reach peak current IBUCKPK during period T1BUCK. Solving Equation 18 on page 12 for inductor LBUCK returns Equation 53: V BST max – V OUT max T1 BUCK 32V – 13.2V 2.3s L BUCK ----------------------------------------------------------------------------------------------- = ----------------------------------------------------------- = 43.
AN379 Step 10) Zero-current Detection Zero-crossings are detected by AC coupling the drain voltage of FET QBUCK to pin BUCKZCD. Capacitor C2 is sized to monitor the zero crossing of a switching drain node. Typical resonant ringing frequencies in the CRD1680 are less than 5MHz. Implying that period Tresonant is greater than 200ns. Series resistor R5 is added to suppress high frequency ringing on the drain node.
AN379 Step 12) Calculate Boost Sense Resistor Sense resistor RBST(Sense) is designed to hit maximum peak current IBSTPK(max) at a threshold voltage VBSTPK(th) equal to 0.33V. From Equation 26 on page 16, calculate sense resistor RBST(Sense) using Equation 62: V BSTPK th 0.33V R BST Sense = -------------------------------- = ---------------- = 0.165 I BSTPK max 2.0A [Eq. 62] where RBST(Sense) = resistor R1 and selected as 0.
AN379 Step 15) Determine Constant Peak Current for Mode2 Sense resistor RBST(Sense) is used to set the maximum peak current for the Mode3 algorithm (see Equation 62 on page 25). The maximum peak current IBSTPK(Mode2) in the boost inductor for the Mode2 is held constant at 2.0 A. Using Equation 32 on page 17, the peak current code IBSTPK(code) for the Mode2 algorithm is set by Equation 67: I BSTPK Mode2 R BST Sense 512 2.0A 0.
AN379 Solving Equation 36 on page 18 for damping capacitance Cdamp yields Equation 71: L leak C rect 2H 1F C damp = ------------------------------------- = --------------------------------- = 1.4F 1.0 R damp [Eq. 71] where Cdamp = damping capacitor C12 and selected as 1F using empirical evidence Step 18) Clamp Circuit The first criteria requires the clamp circuit to dissipate equal amounts of power being produced by the boost stage.
5 Appendix 5.1 Schematic REV DESCRIPTION A.0 INITIAL RELEASE DATE 08/07/13 1127 B.1 1136 B.2 Changing the silicon to B1 and some components values 1153 C.0 ADDED R11 & C12 1165 D.0 ADDED R12 & R16. CHANGED D11/D13,U2,R11,C12 ADDED RED AND BLACK WIRES 09/10/13 10/08/13 11-19-13 12/16/13 FB1 0 Ferrite Bead may be required in place of zero ohm resistor (at FB1) to meet radiated EMI specification. D1 BAS52-02V H6327 BAS52-02V H6327 45V 45V 1 B C5 X7R 0.
AN379REV2 5.2 Dimensions 29 AN379 Figure 7.
AN379 5.3 Bill of Materials BOM: CRD1680-7W-Z Date Generated: 01/07/2014 Line Item Description 0001 CAP 10uF ±10% 25V X7R NPb 1206 Qty UM 2 EA 0002 CAP 27pF ±5% 50V C0G NPb 0603 1 0003 CAP 0.10uF 10% 25V X7RLESR NPb 0603 3 EA EA 0004 CAP 180uF ±20% 35V AL ELEC NPb RAD 1 EA 0005 NO POP CAP NPb 0603 0 EA 0006 CAP 100pF ±5% 50V C0G NPb 0603 1 EA 0007 CAP 1uF ±10% 50V NPb X7R 0805 1 EA 0008 CAP 1000pF ±10% 50V X7R NPb 0603 1 EA 0009 0010 0011 0012 0013 0014 0015 CAP 0.
AN379 Revision History Revision Date REV2 FEB 2014 AN379REV2 Changes Content release for revision B silicon 31
