AN375 Application Note Design Guide for a CS1615 and CS1616 Single Stage Dimmable Offline AC/DC Controller for LED Lamps 1 Overview of the CS1615/16 The CS1615 and CS1616 are high-performance single-stage dimmable offline AC/DC controllers. The CS1615/16 is a cost-effective solution that provides unmatched single lamp and parallel lamp dimmer-compatibility performance for dimmable LED applications.
AN375 IMPORTANT SAFETY INSTRUCTIONS Read and follow all safety instructions prior to using this demonstration board. This Engineering Evaluation Unit or Demonstration Board must only be used for assessing IC performance in a laboratory setting. This product is not intended for any other use or incorporation into products for sale. This product must only be used by qualified technicians or professionals who are trained in the safety procedures associated with the use of demonstration boards.
AN375 2 Introduction This application note is a guide to designing a solid-state lighting (SSL) LED lamp circuit using Cirrus Logic's CS1615/16. The first half of the design guide presents a step-by-step design procedure for calculating the required components for each stage of the system. The second half of the document uses a CRD1615 reference design as an example to verify the design procedure. The CS1615 example is based on the Cirrus Logic CRD1615-8W flyback reference design.
AN375 2.
AN375 3 Design Process The design process for a single-stage power converter system can be partitioned into six circuit blocks (see Figure 1). The AC line voltage is rectified, then passed through an electromagnetic interference (EMI) filter to suppress conducted interference generated by the circuit on the power line. The output of the EMI filter is then converted to the desired DC output by a dual-mode flyback/buck-boost converter.
AN375 3.1 Operating Parameters To initiate the design procedure, a set of operating parameters is required. Operating parameters required for the analytical process are outlined in the table below. Parameters critical to the overall design, but not specifically addressed in this document, include EMI compliance, efficiency, form factor, layout, and operating temperature.
AN375 3.3 Flyback Stage Design Steps for the Flyback Design Flyback Specification Determine IIN(CC) Determine VZener , VReflected, and N Predict T3 and Calculate Duty Cycle 1. Determine the constant input current to achieve full-bright power. 2. Select a FET that aligns with the quality standards of the designer’s company. 3. Determine the transformer turns ratio N from the peak line voltage VINPK, FET breakdown voltage, and reflected voltage VReflected. 4.
AN375 3.4 Flyback Design Figure 3 is a composite timing diagram of the primary and secondary winding currents and switching periods. The flyback design hinges on knowing the peak current IPK flowing through power FET Q4. i(t) Peak Primary Current, IPK Secondary Current Primary Current No Current T1 T3 T2 t TT Figure 3. Timing Diagram of T1, T2, T3, and TT Constant current IIN(CC) is determined by the greater of the TRIAC holding current Ihold or dimmer current Ifb required for full-bright power.
AN375 When operating in Dimmer Mode, the line current must be at least as high as dimmer hold current Ihold. The dimmer hold current is a system parameter. For compatibility with the widest range of dimmers, a value of 60mA is typical for 120V applications, and 40mA is typical for 230V applications. The constant current value used in the design is determined using Equation 4: if Ihold I fb I IN CC = I hold or I IN CC = I fb [Eq.
AN375 Ideally, reflected voltage VReflected should have nearly the same value as peak line voltage VINPK because operating the transformer near 50% duty cycle optimizes the transformer efficiency. Alternatively, zener voltage VZener should be much greater than reflected voltage VReflected to rapidly discharge the energy stored in the transformer leakage inductance.
AN375 allow the RC circuit to respond to the variable dissipation requirements. The RC circuit should be designed to track voltage Vrect. There are many variables associated with the RC snubber circuit design. Many of the variables are not well controlled, therefore the best approach is to start with a conservative value for the RC snubber resistor and increase its value while monitoring the power FET drain voltage at the peak of the line voltage until the highest safe drain voltage is reached.
AN375 Step 6) Calculate Peak Current The switching period TT used in Equation 13 on page 11 is found only at the peak of the minimum input line voltage when reflected voltage VReflected is at its minimum; this value coincides with a useful design point, but it is not yet known whether this corresponds to a minimum or maximum switching frequency. Calculate peak current IPK at minimum duty cycle min using Equation 14: 2 I IN CC I PK = --------------------------- [Eq.
AN375 Step 7) Calculate Primary Winding Inductance Primary inductance LP is calculated to allow sufficient current build up at the 90° point when line voltage VIN is at a peak.
AN375 Step 12) Calculate Primary and Secondary Currents Since the primary and secondary currents have a variable peak and duty cycle across the line voltage phase angle, there is no practical closed-form solution to the RMS value. The RMS/IPK ratio depends primarily on the ratio Z. Figure 6 provides a plot of the ratios P and S relative to primary and secondary, respectively. 30% 28% S 26% Ratio 24% 22% P 20% 18% 16% 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
AN375 Step 14) Dimmer Compatibility Circuit Resistor R15, FET Q2, and associated bias circuit components constitute the recommended dimmer compatibility circuit. The circuit provides a variable current drain to guarantee proper dimmer operation when the flyback current is not sufficient to keep the dimmer from opening prematurely. The SOURCE pin presents a variable current sink to GND controlling the sink current through FET Q2.
AN375 The flyback/buck-boost transformer auxiliary winding monitors output overvoltage and the ZCD function. The auxiliary winding turns ratio must be designed to develop an auxiliary voltage VAUX of approximately 22V peak during period T2 under nominal conditions. The turns ratio for the auxiliary winding is calculated using Equation 23: V F + V OUT NS -------------= --------------------------V AUX N AUX [Eq. 23] The FBAUX pin currents must be limited to less than 1mA.
AN375 Assume using a BJT with a beta equal to 20, then the maximum collector current Icollector is equal to 300mA. The CLAMP pin is driven high a period tp (approximately 300s) prior to the predicted trailing-edge dimmer phase cut.
AN375 4 Design Example The Cirrus Logic CRD1615-8W reference design is used for the design example. The required operating parameters for the analytical process are outlined in the table below. Parameters Output Power Symbol Value POUT 7.0W Tolerance VIN 120V ±10% Output Voltage VOUT 27.
AN375 Reflected voltage VReflected was initially selected to be 170V. To avoid incomplete layers in the transformer winding voltage VReflected was reduced to 165.6V. Use Equation 8 on page 10 to verify the FET breakdown voltage VBreakdown. See Equation 29: V Breakdown = V INPK max + V Zener + V M arg in = 187V + 275V + 138V = 600V [Eq. 29] The low power and cost constraints attached to the design example make the RC snubber circuit a desirable choice.
AN375 Using turns ratio N derived in Equation 36 on page 19, calculate minimum reflected voltage VReflected(min) and maximum reflected voltage VReflected(max). The design chooses a zero tolerance for output voltage VOUT on the assumption that the LED string has a degree of compensation. See Equation 37 and 38: V Reflected min = N V OUT 1.0 + V F = 5.75 27.9V 1.0 + 0.9V = 165.6V [Eq. 37] V Reflected max = N V OUT 1.0 + V F = 5.75 27.9V 1.0 + 0.
AN375 Step 8) Calculate Sense Resistor RSense (R19) Use Equation 16 on page 13 to solve for sense resistance RSense. See Equation 43: 1.4V 1.4V R Sense = ------------ = ------------------------ = 2.73 513.6mA I PK [Eq. 43] Resistor R19 is selected to be a 2.61 standard value. Step 9) Determine RCTRL1 (R13) Use Equation 17 on page 13 to solve for resistance RCTRL1. See Equation 44: 1.4V 4M 1.
AN375 Calculate minimum and maximum period T1 using Equations 50 and 51: L P I PKFREQ max 2.54mH 465mA T1 FREQ min = ------------------------------------------------- = ----------------------------------------------- = 7.7s V INPK min 0.9 2 120 [Eq. 50] L P I PKFREQ min 2.54mH 285mA T1 FREQ max = ------------------------------------------------ = ----------------------------------------------- = 24s 30V V Start [Eq.
AN375 Step 16) Zero-current Detection The recommended design approach is to set the auxiliary voltage VAUX to 22V. A higher voltage is acceptable to assure a stable steady state supply voltage VDD at a cost of slightly larger losses. The customer reference design CRD1615-8W is designed with a 5.75:1:1 transformer ratio, hence the auxiliary voltage VAUX is designed to be equal to the output voltage VOUT. Use Equation 23 on page 16 to calculate the turns ratio for the auxiliary winding.
5 Appendix 5.1 Schematic 5(9 / X+ 6 ( 5 2KP %5 +' 7 9 607 */$66 %5,'*( 5(&7 ) 1 5 . : & 3/<)/0 X) /,1( & 07/ 32/< 8) 5 5 N 95 029 ' . 9 &+*' & 72 3$1$621,& &+*' 5 72 2+06 $''(' 9 P$ 7(;7 &+*' &211(&7,21 21 / % )520 *1' 72 /(' 9( &+*' 8 )520 5(9 % 72 5(9 $ % (&2 & 5(029(' 7+(50$/ 3$' )520 8 5 2+0 5 .
AN375REV4 5.2 Dimensions 25 AN375 Figure 9.
AN375 5.3 Bill of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Rev DescripƟon DIODE RECT 200V 0.8A NPB MINIDIP CAP 33uF ±20% 35V ALUM ELEC NPb RAD CAP 0.1uF ±10% 250V MPET NPb RAD CAP 56pF ±5% 50V C0G NPb 0603 CAP 680uF ±20% 35V AL ELEC NPb RAD A CAP 0.047uF ±10% 25V X7R NPb 0603 CAP 100pF ±5% 50V C0G NPb 0603 CAP 2200pf ±10% 2KV X7R NPb 1210 CAP 0.1uF ±10% 25V X7R NPb 0603 CAP 0.047uF ±5% 250V POLY NPb RAD CAP 0.
AN375 Revision History Revision Date REV1 DEC 2012 Initial release. REV2 FEB 2013 Changed content to align with production CRD1615-8W. REV3 MAR 2013 Context clarification. REV4 JUL 2013 Content updated using PCBA Rev C.
