AN372 Application Note Design Guide for a CS1612 and CS1613 Dimmer-compatible SSL Circuit 1 Overview of the CS1612/13 The CS1612 and CS1613 are digital control ICs engineered to deliver a high-efficiency, cost-effective, flicker-free, phase-dimmable, solid-state lighting (SSL) solution for the incandescent lamp-replacement market. The CS1612/13 is designed to control a quasi-resonant buck topology. The CS1612 and CS1613 are designed for 120VAC and 230VAC line voltage applications, respectively.
AN372 IMPORTANT SAFETY INSTRUCTIONS Read and follow all safety instructions prior to using this demonstration board. This Engineering Evaluation Unit or Demonstration Board must only be used for assessing IC performance in a laboratory setting. This product is not intended for any other use or incorporation into products for sale. This product must only be used by qualified technicians or professionals who are trained in the safety procedures associated with the use of demonstration boards.
AN372 2 Introduction This application note provides a guide to designing a Solid State Lighting (SSL) LED lamp circuit using Cirrus Logic's CS1612/13. The first half of the document presents a step-by-step design procedure for calculating the required components for each stage of the system. The second half of the document supports the design effort by showing an example of a CS1613 design. See the CS1610/11/12/13 TRIAC Dimmable LED Driver IC data sheet for more details about the CS1612/13 IC. 2.
AN372 3 Design Process The design process for a two-stage power converter system can be partitioned into six circuit blocks (see Figure 1). The AC line voltage is passed through an electromagnetic interference (EMI) filter to suppress conducted interference found on the power line. The output of the EMI filter is then converted to the desired DC output by a boost-buck converter. The power converter system includes the Gate Bias, Steady State Supply, and Active Clamp support circuitry.
AN372 3.2 Overview of Design Steps The CS1612/13 LED driver IC controls a power converter system that has two distinct power-conversion stages. The IC requires supporting circuitry to provide a steady-state power supply with gate bias, a clamp circuit, and EMI filtering. The recommended design process is outlined below: 1. Start with the buck stage. 2. Design for full power at minimum VBST. Note that any design may require trade-offs for different operating parameters. 3.
AN372 3.3 Buck Stage Design Figure 2 illustrates the steps for designing the buck stage. Buck Specification Steps for the Buck Design 1. Select a buck topology Determine N, Fsw, V Reflected, and VCLAMP 2. Set the boost output voltage, VBST. 3. Select a FET that aligns with the quality standards of the designer’s company. Estimate T3 Calculate TTfb 4. Determine the inductor turns ratio from the VBST, FET voltage, and reflected voltage, VReflected. 5.
AN372 Step 1) Choosing a Buck Topology The first step in designing the buck stage is to choose a tapped buck or a normal buck.
AN372 Figure 3 illustrates a generic implementation of a buck converter using a tapped inductor topology. A normal buck stage can be implemented by neglecting the N turn's extension. The load is composed of a string of LEDs. Diode D3 is the catch diode, also known as the free wheeling diode, and its function is to allow the current to flow in inductor L4 and to the load after FET Q4 opens.
AN372 The buck stage is supplied by the boost output voltage. The boost output voltage is regulated within 10% by the boost stage. The buck control loop regulates the output current as long as the peak current has sufficient margin to rise 10% at the lowest boost output voltage. Figure 4a and Figure 4b show idealized waveforms of the FET Q4 drain voltage and drain current and the diode D3 current.
AN372 Step 2) Select a Value for Boost Output Voltage The value of the boost output voltage, VBST, must be greater than the maximum input AC line voltage peak. The maximum VBST voltage, VBST(max), should be kept as low as possible to help maintain the FET breakdown requirement within economical constraints. VBST is determined by an internal parameter and changes slightly depending on the type of dimmer detected. With sense resistors R7, R8, R14, and R15 set to 1.
AN372 For optimum efficiency, the increase in conduction losses (created by an uneven duty cycle) must balance the reduction of the losses caused by discharging the leakage inductance (obtained by increasing the overshoot voltage). Equation 3 is used to balance all voltages contributing to the FET voltage drain and source. V Breakdown = V BST + V Reflected + V CLAMP – V Reflected + V M arg in [Eq.
AN372 current flows in the load circuit, dilutes the energy delivered during time T1 and T2 resulting in lower average power to the load. VDS t T1 T2 T3 Figure 6. Timing Diagram of Times T1, T2, T3, and TT Dimming Operation The dimmer conduction time or phase cut information is extracted by the boost stage and supplied to the buck stage as a digital parameter, dim, ranging from 0.02 to 1 as a measure of the normalized output power to be delivered.
AN372 Initially, T3 is assumed to be zero. After the circuit is built, the oscillation period can be measured, and the circuit parameters can be tuned to assure full power at the nominal switching frequency. Setting T3 to zero defines the total switching period TT as: TT = T1 + T2 [Eq. 8] solving for the critical duty cycle C using Equation 7 and Equation 8 yields: V OUT N + 1 T1 C = ------- = ------------------------------------------------- N V OUT + V BST TT [Eq.
AN372 Step 9) Calculate the Buck Inductance (as Measured Across the N+1 Turns) V BST – V OUT T1 L = ---------------------------------------------------I PK FB [Eq. 15] Step 10) Calculate RFBGAIN (R17) Use Equation 16 to calculate the second-stage gain resistor RFBGAIN (R17). 62.5k R FBGAIN = -----------------------------------TT fb ---------- T2 fb 2 – 1 [Eq.
AN372 Step 14) Circuit Adjustments Circuit adjustments are required after the inductor has been designed and constructed. Recalculate resistor RFBGAIN using Equation 16. The second-stage gain, FBGain, is an internal constant that is programmable by resistor RFBGAIN. V BST + N V OUT TT fb FB Gain = ----------- = ------------------------------------------------T2 fb V BST – V OUT [Eq. 20] FBGain is used in the second-stage algorithm to control the switching period, TT.
AN372 Notes on Circuit Fine Tuning • Going beyond the RFBGAIN limitation will not have any further effect on the design. • RSense and RFBGAIN are frequently adjusted simultaneously to reach the desired operating point. • The optimized final design will have a slightly different switching frequency variation than the first design iteration. • When the load is increased or decreased by 10%, then RSense needs to be decreased or increased by less than 10%, respectively.
AN372 3.4 Boost Stage Design The design process for the boost stage is outlined below: 1. Determine IPK(BST) and a tentative resistor value, RIPK (R13) 2. Determine boost inductor specifications 3. Calculate boost input and output capacitors The boost stage is designed in No-dimmer Mode, which has a considerable degree of freedom in its design parameters. For the boost stage to operate in dimmer mode and with the largest variety of dimmers, the design is constrained within a more limited set of parameters.
AN372 The AC line current does not follow the inductor peak current envelope because the circuit operates in CRM and DCM. The switching frequency and duty cycle changes across the AC line phase resulting in a changing average value after the EMI filter smoothing. 0.14 AC Line Current Inductor Peak Current 0.12 0.10 Current (A) 0.08 0.06 0.04 0.02 0.00 0 15 30 45 60 75 90 105 120 135 150 165 180 Phase Angle (°) Figure 9.
AN372 The frequency range should be as high as possible without exceeding 75kHz. This strategy will keep the fundamental and second harmonic below the 150kHz EMI requirements. 140 120V Min Freq 130 120V Max Freq Switching Frequency (kHz) 120 230V Min Freq 110 230V Max Freq 100 90 80 70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 Power Multiplied by Inductance (Watts Multiplied by mH) 120 130 140 Figure 10.
AN372 Step 19) Determine Boost Input Capacitor To be compatible with a wide range of dimmers, the boost input capacitance should be minimized. Large input capacitance impacts the ability of the controller to properly sustain the current required by the dimmer and may cause oscillation. Capacitors should not be connected to the AC line side of the bridge rectifier. Added AC lineside capacitance alters the dimmer behavior in multi-lamp configurations and shifts the dimming curve.
AN372 The BSTAUX pin and FBAUX pin currents must be limited to less than 1mA. A series resistor of at least 22 k must be used to limit the current. Step 23) Overvoltage Protection Output open circuit protection and output overvoltage protection (OVP) are implemented by monitoring the output voltage through the buck inductor auxiliary winding. During switching time T2, the voltage across the buck inductor L4 auxiliary winding is representative of the output voltage using a turns ratio relationship.
AN372 Solving Equation 29 for CODE: N 2 V CONNECT th CODE = ------------------------------------------------------------------I CONNECT R NTC + R S 256 1.25 V = ---------------------------------------------------------- 80A R NTC + R S [Eq. 30] 4M = -------------------------------- R NTC + R S The tracking range of this resistance ADC is approximately 15.5k to 4M.
AN372 Step 25) Clamp Circuit To keep dimmers conducting and prevent misfiring, a minimum power needs to be delivered from the dimmer to the load. This power is nominally around 2W for 230V and 120V TRIAC dimmers. At low dim angles (≤90°), this excess power cannot be converted into light by the output stage because of dim mapping at light loads. VBST can rise above the safe operating voltage of the primary-side bulk capacitor C4.
AN372 4 Design Example The required operating parameters for the analytical process are outlined in the table below. Parameters Symbol Value POUT 9.6W VIN 230V VOUT 24V 5% IOUT 400mA Fsw(max) 125kHz Output Power AC Line Input Voltage Output Voltage Load Current Maximum Switching Frequency* * Increasing FSW reduces the size of the magnetics but increases switching losses in the FET. 4.
AN372 The maximum FET voltage is calculated using Equation 38: V DS max = V BST max + V OUT max + V D3 = 405 V + 40.5V + 24 V + 1.2V + 1V = 471.7V [Eq. 38] where VD3 = Forward voltage across catch diode D3. Examining the result reveals two problem areas: 1. The FET peak current IPK(FB) is 30 times the average current IAV, requiring the FET to carry and switch a substantial current. 2. Period T1 is short, just under 0.5s.
AN372 For practical winding reasons an integer turns ratio is preferred giving the option of multifilar winding taking advantage of tight coupling. The maximum FET voltage VDS is calculated using Equation 44. V DS = V BST max + N V OUT max = 445V + 4 25.2 V = 546V [Eq. 44] Step 5) Select the Full Brightness Switching Frequency Minimum and maximum duty cycles, for the tapped buck, are calculated using Equation 9: V OUT min N + 1 23.
AN372 Choosing a 6.49Ω standard value will assure margin against resistor tolerance. To prevent false triggering by the comparator, pin FBSENSE has an internal blanking time of 550ns. To reduce switching spikes, it is recommended to add an additional RC filter circuit using a 1k resistor followed by a 100pF capacitor. Step 9) Calculate the Buck Inductance (as Measured Across the N+1 Turns) The buck inductance L is the inductance of the entire (N+1) winding.
AN372 Step 13) Buck Inductor Specification Specifications for the buck inductor L4 can now be compiled to enable suppliers to design within size and cost constraints. Parameter Value Output DC Power 10.1W Converter Topology CRM Buck Switching Frequency 125kHz 3.8 mH 10% Primary Inductance Peak Current in the (N+1) Turn Winding 0.207A RMS Current in the N-turn Winding 62mA Turn Ratio N:1 4 RMS Current in the 1-turn Winding 0.
AN372 Boost inductor RMS current IRMS depends on the AC line RMS current, the triangular shape, and the stepped envelope. As a first approximation, consider the inductor RMS current to be equal to 1.25 times the AC line RMS current. P IN 1.25 10.1W 1.25 I RMS = --------- ----------- = ----------------- -------------- = 61mA PF V IN 0.9 230V [Eq. 63] Calculate the auxiliary winding turn ratio using Equation 64. NP 405 -------------= ---------- = 18.4 N AUX 22 [Eq.
AN372 The negative voltage on the auxiliary winding is calculated using Equation 67: Z 0.4 – V BST – V OUT ------------------ = – 445V – 23.8V -------- = – 33.7V 5 N + 1 [Eq. 67] The recommended current into pin FBAUX is limited to 1mA. Choosing resistor R12 to equal 47k limits the current to 0.72mA. To set the OVP, R13 must be chosen, yielding Equation 68: R12 R13 ---------------------------= ---------- 29 – 1.25 1.25 [Eq. 68] where R13 = 2.
AN372 action. At 125°C the thermistor has 2.5k plus resistor R18 = 14k present a resistance of 16.5k at pin eOTP, reaching the point at which a thermal shutdown fault intervenes. Step 25) Clamp Circuit Clamp load resistors R6 and R16 must each be 2k2W resistors for 230V systems. This value has been validated for optimal dimming performance. The design process assumed T3 = 0.
AN372 Revision History 32 Revision Date REV1 AUG 2012 Changes Initial Release.
