AN368 Application Note Design Guide for a CS1630/31 2-Channel TRIAC Dimmable SSL Circuit 1 Overview of the CS1630 The CS1630 is a high-performance offline AC /DC LED driver for dimmable and high color rendering index (CRI) LED replacement lamps and luminaires. It features Cirrus Logic’s proprietary digital dimmer compatibility control technology and digital correlated color temperature (CCT) control system that enables two-channel LED color mixing.
AN368 IMPORTANT SAFETY INSTRUCTIONS Read and follow all safety instructions prior to using this demonstration board. This Engineering Evaluation Unit or Demonstration Board must only be used for assessing IC performance in a laboratory setting. This product is not intended for any other use or incorporation into products for sale. This product must only be used by qualified technicians or professionals who are trained in the safety procedures associated with the use of demonstration boards.
AN368 TABLE OF CONTENTS 1 OVERVIEW OF THE CS1630 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.
AN368 Step 9) Boost Inductor Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 10) Determine Boost Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 11) Determine Boost Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Completing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN368 c. Tune IPK(FB) Compensations for Optimum Linear Performance . . . . . . . . . . . . . . . . . . . . . . d. Set T2 Offset Delays to Get Optimum Linear Performance . . . . . . . . . . . . . . . . . . . . . . . . . . e. T2 Commutation Time Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f. Procedure for Measuring the Second-stage Output Current Regulation . . . . . . . . . . . . . . . . Step 6) Synchronizer Circuit Design . . . . . . . . . . . . . . . . . . .
AN368 2 Introduction This application note provides a guide to designing a solid-state lighting (SSL) LED lamp circuit using Cirrus Logic's CS1630. The second-stage topology is a flyback topology with a series LED lamp stack as the output configuration. The first half of the document presents a step-by-step design procedure for calculating the required components for each stage of the system. The second half of the document supports the design effort by showing an example of a CS1630 design.
AN368 2.
AN368 2.
AN368 3 Design Process The design process for a two-stage power converter system can be partitioned into seven circuit blocks (see Figure 1). The AC line voltage is passed through an electromagnetic interference (EMI) filter to prevent injection of switching noise from the driver into the power line. The output of the EMI filter is then converted to the desired DC output by a boost PFC followed by a flyback converter.
AN368 3.2 Design Process The design process requires a specification covering the required operating range, color temperature, dimmer compatibility, form factor, and applicable standards.
AN368 3.3 Design Procedure Step 1) Select Input Voltage The CS1630 is optimized for 120VAC line voltage applications and designs targeting 108 to 132 VAC markets. Step 2) Design for a Flyback Topology The light engine is defined for a flyback topology in a series configuration. Figure 2 illustrates a flyback topology with a series lamp configuration.
AN368 Step 3) Determine Second-stage Parameters for a Flyback Topology Figure 3 illustrates the steps for designing the second stage. Second Stage Flyback Specifications Steps for the Flyback Design Determine N, Fsw, V Reflected, and VCLAMP 1. Set the boost output voltage, VBST. 2. Select a MOSFET that aligns with the quality standards of the designer’s company. 3. Determine the transformer turns ratio from the VBST, FET voltage, and reflected voltage, VReflected. Estimate T3 Calculate TTfb 4.
AN368 a. Set the Value for Boost Output Voltage The value of the boost output voltage VBST must be greater than the maximum input AC line voltage peak. The maximum VBST voltage VBST(max) should be kept as low as possible to help keep the FET breakdown requirement within economical constraints. VBST is determined by an internal parameter and changes slightly depending on the type of dimmer detected.
AN368 For optimum efficiency, the increase in transformer losses (created by an uneven duty cycle) must balance the reduction of the losses caused by discharging the leakage inductance (obtained by increasing the overshoot voltage). Equation 3 is used to balance all voltages contributing to the FET voltage drain and source. [Eq. 3] V Breakdown = V BST max + V Zener + V M arg in where, VOvershoot = VZener - VReflected c.
AN368 The minimum switching frequency Fsw(min) for the second stage is configured to provide good power regulation. The minimum switching frequency should be set to the smallest possible value, but it should remain outside of the audible frequency range. Fsw(min) is configured using register TTMAX at Address 38. Bits TTMAX[7:0] set the maximum allowable target period for the second-stage time TT: 1 -------------------- = TTMAX[7:0] 128 + 127 50ns F sw min [Eq.
AN368 Calculate Mode 1 duty ratio DMODE1 and Mode 2 duty ratio DMODE2 using Equations 11 and 12, respectively: N V MODE1 D MODE1 = -------------------------------------------------------- V BST + N V MODE1 [Eq. 11] N V MODE2 D MODE2 = -------------------------------------------------------- V BST + N V MODE2 [Eq.
AN368 Calculate the MOSFET ‘OFF’ time T2CH1 in Mode 1 using Equation 22: T2 CH1 = TT CH1 – T1 CH1 – T3 CH1 [Eq. 22] Calculate the MOSFET ‘OFF’ time T2CH2 in Mode 2 using Equation 23: T2 CH2 = TT CH2 – T1 CH2 – T3 CH2 [Eq. 23] f.
AN368 The RMS current in the secondary winding ISEC(RMS) is calculated using Equation 30: I SEC RMS = 1 – D MODE1 1 – D MODE2 2 2 2 2 N I PK1 FB ----------------------------+ N I PK2 FB ---------------------------- 3 3 [Eq. 30] i. Calculate RSense (R21) A scaling factor is used to provide for a margin to account for manufacturing tolerances of external components, such as inductance and resistance tolerance.
AN368 The FBAUX pin current must be limited to less than 1mA. Resistor R22 plus resistor R23 should be chosen such that current VAUX /(R22 + R23) is less than 1mA during the time when FET Q5 is ‘ON’ or ‘OFF’. A series resistor of at least 22k must be used to limit the current. Bit VALLEYSW in register Config2 at Address 34 configures the quasi-resonant switching (valley switching) on the second stage. To enable valley switching, set bit VALLEYSW to ‘1’.
AN368 m. Recalculate RSense The flyback primary current is controlled by comparing the voltage across RSense at pin FBSENSE to an internal threshold of 1.4V. To guarantee the rated LED current under worst-case conditions, when the LED string has maximum voltage, the VBST is at its minimum point and RSense is at its highest tolerance. Adjust RSense to obtain the nominal LED current using Equations 31 and 32.
AN368 c. Trailing-edge Blanking Configurable blanking time on the zero-current detection (ZCD) comparator provides protection to suppress false comparator values due to noise at the falling edge of the gate drive. The controller suppresses any comparator result from the falling edge of the gate drive to the end of the configurable trailing-edge blanking time. The duration of the trailing-edge blanking time is set through the TEB[3:0] bits in register Config18 at Address 50.
AN368 g. Automated Resonant Period Measurements To ensure accuracy of the T2 duration measurements within the CS1630 controller, the resonant period TRES of the power train can be automatically measured during the T3 time (secondary current equals zero) of the switching cycle. To enable the automated resonant period measurement, set the PROBE bit within register Config7 at Address 39 to a value of ‘1’.
AN368 h. Switching Frequency Across Dim Range From the equations below and setting the OTP registers as follows, the switching frequency across the dim range can be calculated. A sample plot of the switching frequency across dim values is shown in Figure 7. 35 30 A B Frequency (kHz) 25 20 C 15 10 D 5 0 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 Dim Figure 7.
AN368 Frequency in Region C In Region C, the switching frequency is kept constant, and the peak current IPK(FB) starts to reduce. Period TTC is calculated using Equation 46: TT C = 50s [Eq. 46] Frequency in Region D Once the peak current IPK(FB) reaches its minimum value, the switching frequency continues to reduce until the minimum peak current limit is reached, or the minimum switching frequency set by the maximum switching period register TTMAX at Address 38.
AN368 The linearity of the second-stage current regulation is determined by the error between the expected currents at any given dim level and the measured currents at that dim level. Percentage error Ierror at any particular dim is given by Equation 50: I calculate – I measure [Eq.
AN368 c. Tune IPK(FB) Compensations for Optimum Linear Performance To achieve high accuracy for the output current, it is essential to obtain a highly accurate peak current IPK(FB). Time T1 compensation T1comp is used to factor in the peak overshoot of the inductor current due to the current sense comparator delay and other path delays involved in turning ‘OFF’ the FET. If IPKx(REF) is the desired peak current, the actual peak can be adjusted using the CS_DELAY[2:0] bits in register Config60 at Address 92.
AN368 d. Set T2 Offset Delays to Get Optimum Linear Performance A delay is present between the time the primary current reaches zero and the transfer of actual power to the load, as shown in Figure 9. Correct measurement of the actual T2 time is important for the regulation loop to help reduce errors in output current across the dim range. GD 0 t VDrain VBST 0 t VAUX 0 t ZCD Comparator Output VZCD 0 t IPRI 0 t IOUT 0 Td1 T2 T2RES t Td2 T2raw Figure 9.
AN368 Time T2CHx offset delays cause errors when calculating average current regulation using Equations 27 and 28. Averaged output current IMODEx of a flyback converter is illustrated in Figure 10. IP RI IMODE x TX1 VB S T Z3 Snubber Channel 1 LED (White) C8 D2 Synchronizer Circuit CP Q3 VDrain CS1630 /31 C15 GD FBAUX FBSENSE Q5 13 15 D15 V A UX 11 VMODE x D5 Channel 2 LED (Red) IGND IS ense GND 12 RS ens e R22 Zero-cross Detection R23 GND Figure 10.
AN368 Times T2CH1OFF and T2CH2OFF are offset delays that assist in achieving the desired linear performance on the output currents across dim on the second stage (see Figure 11). Current through the secondary = 0 VDrain = VBST Pin FBAUX = 200mV V Pin FBAUX = 0V Comparator trips System is at the valley VBST VDrain 200mV 0V FBAUX COMPARATOR t TCHxZCD(Delay) TCHxOFF TRES 4 Figure 11.
AN368 e. T2 Commutation Time Delay Compensation The presence of circuit parasitic components, such as leakage inductance, causes a delay between the time the primary current becomes zero and the power actually being transferred to the load. This delay is shown in the following illustration: Point at which pin FBAUX equals 200mV FBAUX GD Tdt2 Tdt2’ Figure 12.
AN368 f. Procedure for Measuring the Second-stage Output Current Regulation This step describes the procedure for measuring the second-stage output current on both channels across the operable dim range of the system. Once this data is available, the error can be characterized in the secondstage current regulation, as described in the previous section. 1. Connect to the LED driver board using the CS1630 I2C communication port. 2.
AN368 3. Disable the color system and boost stage by forcing gains GAINDR and GAINDTR to a value of 1 and the converter to a flyback-only stage. This can be done by the following commands: i. Write 0x40 to Address 210 (forces the color gain for channel 1 in 2.8 unsigned format). ii. Write 0x40 to Address 211(forces the color gain for channel 2 in 2.8 unsigned format). iii.
AN368 b. Flyback Mode Operation Using a Dual LED String Synchronizer Circuit The dual-LED string load is implemented in a series output configuration. The series configuration is illustrated in Figure 13. In the series configuration, the white LED string is always on. The red LED string is on when FET Q3 is turned ‘OFF’ and is shorted out when FET Q3 is turned ‘ON’. The Synchronizer Circuit controls the switching between the two lamp strings.
AN368 Component U2 is a positive edge D-type flip-flop and is used as a frequency divider. The output terminal Q is connected to input D. The CLK signal acts as a clock signal, and the output Q changes on the positive edge on the CLK signal. When Q is high, FET Q3 is turned ‘ON’, and the red LED string is shorted out. When Q is low, FET Q3 is turned ‘OFF’, and charge is delivered to the red LED string. GD VL Vsync Dual Gate Figure 15.
AN368 c. Synchronizer Circuit RC Filter Design The Synchronizer Circuit has an RC filter in the feedback path from Q to D. This circuit should be tuned for optimum synchronizer performance in the event of noise events on the clock at low dim angles (see Figure 16). The noise events are design dependent and should be reviewed when major changes occur in the secondary power train (that is, the inductor or transistor).
AN368 One of the LED strings is composed of red or amber LEDs, and the other string is composed of cool-white or blue-white LEDs. While the lumen output of white LEDs does not vary significantly across temperature, the lumen output of red LEDs can vary as much as 40% across temperature. To achieve a stable light output, the current in the red LED string needs to be compensated with respect to temperature. This is accomplished by the color control block (see Figure 17).
AN368 3.4 Boost Stage Design The design process for the boost stage is outlined below: 1. Determine IPK(BST) and a tentative IPK(BST) OTP setting 2. Determine Boost Inductor Specifications 3. Calculate Boost Input and Output Capacitors The boost stage is designed in No-dimmer Mode, which has a considerable degree of freedom in its design parameters. For the boost stage to operate in dimmer mode and with the largest variety of dimmers, the design is constrained within a more limited set of parameters.
AN368 The AC line current does not follow the inductor peak current envelope because the circuit operates in CRM and DCM. The switching frequency and duty cycle changes across the AC line phase, resulting in a changing average value after the EMI filter smoothing. 0.14 AC Line Current Inductor Peak Current 0.12 0.10 Current (A) 0.08 0.06 0.04 0.02 0.00 0 15 30 45 60 75 90 105 120 135 150 165 180 Phase Angle (°) Figure 18.
AN368 The frequency range should be as high as possible without exceeding 75kHz. This strategy keeps the fundamental and second harmonic below the 150kHz EMI requirements. 140 120V Min Freq 130 120V Max Freq Switching Frequency (kHz) 120 230V Min Freq 110 230V Max Freq 100 90 80 70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 Power Multiplied by Inductance (Watts Multiplied by mH) 120 130 140 Figure 19.
AN368 Step 10) Determine Boost Output Capacitor The boost stage output capacitor is also the flyback stage input capacitor. Determine the size of the boost output capacitor using the following points: • For a 120V line input system, capacitor C6 > 2F/Watt of input power • For a 230V line input system, capacitor C6 > 0.
AN368 Step 14) Boost Zero-current Detection The CS1630 uses zero-current detection (ZCD) to minimize switching losses. The ZCD algorithm is designed to turn ‘ON’ the FET when the resonant voltage across the FET is at a low point. Valley switching reduces the CV2 power losses associated with rerouting charge from the body capacitance of the FET. Similar approaches are taken when turning ‘ON’ the boost FET Q1 and the flyback FET Q5.
AN368 b. Overcurrent Protection Overcurrent protection (OCP) is designed to detect when the current-sensing resistor RSense is open circuited or unusually large. Overcurrent protection is implemented by monitoring the voltage across the sense resistor RSense. The voltage applied to pin FBSENSE is fed to a comparator and measured against a threshold voltage VOCP(th) of 1.69V.
AN368 4. Configure the threshold for the OLP event accumulator used to declare an OLP fault. Bits OLP_CNT[2:0] in register Config49 at Address 81 are used to configure the threshold. If the voltage on pin FBSENSE does not exceed 200mV within 250ns after the second-stage gate drive turns ‘ON’ and the OLP blanking time elapsed, then the OLP event accumulator is incremented by 1, and the gate drive is disabled.
AN368 e. Short Circuit Protection Short circuit protection (SCP) is designed to detect when either of the channels is short circuited and prevents the second stage from operating in continuous current mode (CCM). The charge regulation loop is monitored using a digital algorithm that detects SCP events and is enabled when bit SCP is set to ‘0’. Bit SCP is bit 1 in register Config16 at Address 48. f.
AN368 h. Clamp Overpower Protection Clamp overpower protection (COP) is designed to detect when the boost voltage exceeds a specified threshold. Clamp overpower protection is implemented by monitoring the boost output voltage applied to the bulk capacitor connected to the boost output. The voltage applied to pin BSTOUT is measured against a programmable threshold voltage VBOP(th).
AN368 j. External Overtemperature Protection The external overtemperature protection (eOTP) pin is used to implement overtemperature protection using a negative temperature coefficient (NTC) thermistor. The total resistance on the eOTP pin is converted to an 8bit digital ‘CODE’ (which gives an indication of the temperature) using a digital feedback loop, adjusting the current ICONNECT into the NTC and series resistor RS to maintain a constant reference voltage of 1.25V (VCONNECT(th)).
AN368 When exiting reset, the chip enters startup and the ADC quickly (<5ms) tracks the external temperature to check if it is below TempWakeup reference code CODEWakeup before the boost and second stages are powered up. If this check fails, the chip waits until this condition becomes true before initializing the rest of the system. Current (ILED, Nom.
AN368 5. The first filtered output is compared against a programmable code value that corresponds to the desired shutoff temperature set point TempShutdown and is set using bits SHUTDWN[3:0] in register Config58 at Address 90. The shutdown temperature code is configured as an offset from the wakeup temperature code; TempeOTP < TempWakeup < TempShutdown. See Equation 79: CODE TEMPShutdown = CODE TEMPWakeup + SHUTDWN [3:0] 4 [Eq. 79] 6.
AN368 9. Configure the second-stage dim level adjustment using the external temperature. The external NTC connected to the eOTP pin is used to measure the temperature.To enable the adjustment process, bit DIM_TEMP in register Config58 at Address 90 is set to ‘1’. 10. Set the lower saturation limit for the 8-bit temperature code provided to the color system from the fast low-pass filter before it is used for polynomial computations.
AN368 The EMI filter and the reactances associated with the dimmer constitute a complex reactive network that has minimal damping. This reactive network will ring as it is excited by the dimmer turn on and the boost stage conduction. If the current in the dimmer's TRIAC reverses, the TRIAC opens, which disturbs the dimmer timing and causes flicker. For this reason stringent limitations are imposed on the values assigned to the EMI components. a.
AN368 Step 18) Layout Basics for any power layout are as follows: • Keep power traces as short as possible. • Keep the controller away from power components and traces if possible. Keep sensitive traces (all sense inputs) away from high dv/dt traces such as FET drain, FET gate drive, and auxiliary windings. • Isolate control GND from power GND. - All control components must be grounded to SGND.
AN368 4 Design Example The Cirrus Logic CRD1630-9W reference design is used for the design example. The required operating parameters for the analytical process are outlined in the following table. Parameter Symbol Value POUT 7.0W AC Line Voltage (nominal) VIN 120V Channel 1 Output Voltage VCH1 9.7V Channel 2 Output Voltage VCH2 10.
AN368 It is recommended to choose VReflected to equal 37% of VZener. Voltage VReflected is set to 116.6V, leaving 183V overshoot to dissipate as leakage inductance energy. The actual overshoot range is from 65V to 95V, depending on the clamp zener tolerance. See Equation 82: V Breakdown = V BST max + V Zener + V M arg in = 220V + 315V + 65V = 600V [Eq. 82] c. Determine the Flyback Transformer Turns Ratio Calculate a turns ratio N using Equation 4: V Reflected 116.
AN368 e. Determine the Flyback Nominal Timing T1 and T2 Calculate Mode 1 duty ratio DMODE1, and Mode 2 duty ratio DMODE2, using Equations 11 and 12, respectively: N V MODE1 5.57 20.95V - = ----------------------------------------------------------------- = 0.37 D MODE1 = -------------------------------------------------------- V BST + N V MODE1 200V + 5.57 20.95V [Eq. 90] N V MODE2 5.57 10.4V - = ------------------------------------------------------------- = 0.
AN368 Calculate the MOSFET ‘ON’ time T1CH1 in Mode 1 using Equation 20: T1 CH1 = TT CH1 – T3 CH1 D MODE1 = 14.29s 0.37 = 5.3s [Eq. 99] Calculate the MOSFET ‘ON’ time T1CH2 in Mode 2 using Equation 21: T1 CH2 = TT CH2 – T3 CH2 D MODE2 = 18.76s 0.22 = 4.2s [Eq.100] Calculate the MOSFET ‘OFF’ time T2CH1 in Mode 1 using Equation 22: T2 CH1 = TT CH1 – T1 CH1 – T3 CH1 = 15.29s – 5.3s – 1s = 9.0s [Eq.
AN368 h. Determine the RMS Current in the Winding The RMS current in the primary winding, IPRI(RMS), is calculated using Equation 29: I PRI RMS = D MODE1 D MODE2 2 - + I 2PK2 FB ------------------I PK1 FB ------------------ 3 3 = 0.37 0.225 2 2 299mA ----------- + 237mA --------------- 3 3 [Eq.108] = 123.
AN368 The FBAUX pin current must be limited to less than 1mA. Resistor R22 plus R23 should be chosen such that current VAUX /(R22 + R23) should be less than 1mA during the time when FET Q5 is ‘ON’ or ‘OFF’. A series resistor of at least 22k must be used to limit the current. k. Determine Output Capacitors Channel 1 output capacitor C8 ripple current IRipple(RMS) is the vectorial difference between transformer TX1 secondary current and the DC load current. See Equation 113. I Ripple RMS = 2 2 [Eq.
AN368 m. Recalculate RSense Once the current sense resistor RSense value is determined, the target output current CH1CUR for channel 1 is calculated using: 511 2 R Sense I CH1 CH1CUR = -----------------------------------------------------N V Sense 511 2 4.28 488mA = --------------------------------------------------------------5.57 1.4V [Eq.
AN368 e. Minimum Measurable Peak Current The minimum peak current level bits IPEAK[2:0] in register Config3 at Address 35 are set to ‘100’ and the offset adjustment bits CLAMP[1:0] in register Config2 at Address 34 are set to ‘01’. Voltage VIPK(min) is calculated using Equation 41. IPEAK[2:0] + 1 16 + 15 – CLAMP[1:0] 8 + 8 V IPK min = 1.
AN368 2. Disabling automatic TRES probing and fixing the TRES probe count will resolve the problem. This has the disadvantage that if the resonant frequency differs by a lot due to board-to-board or component-to-component variations, then the fixed value will not be accurate. Step 5) Optimize Output Current Regulation a.
AN368 f. Procedure for Measuring the Second-stage Output Current Regulation Measurement of second-stage output current regulation is required even though T2 commutation time delay compensation is disabled. The tuning process has accounted for all the circuit parasitics that cause errors in the output current regulation. The final step is to measure the output current regulation as described in Step 4f Procedure for Measuring the Second-stage Output Current Regulation on page 31.
AN368 Design Tip - Frequent re-syncing events on the second stage Symptoms: The current in either channel keeps changing by 1mA to 3mA in either direction and does not stay fixed. Attaching a current probe on the output shows random large droops in the red channel current waveforms (cyan) as shown below or non-steady behavior in the blue-white current (purple). The droops will span across multiple switching cycles if they are triggered by a re-sync event. Figure 22.
AN368 The minimum dim setting for the second stage is configured using the S2DIM register at Address 37. The enforced minimum dim percentage dimmin is determined by Equation 59: S2DIM[7:0] 16 + 15 dimmin = -------------------------------------------------------- 100 4095 8 16 + 15 = --------------------------- 100 4095 [Eq.131] = 3.
AN368 The PEAK_CUR register at Address 51 is used to store IPK(code). Maximum power output is proportional to IPK(code). Using Equation 133, calculate IPK(code): I PK BST - = 273mA ------------------- = 66.6 I PK code = ------------------4.1mA 4.1mA [Eq.133] The PEAK_CUR register is set to ‘01000100’. Current ISAT is a constant value of 0.6A and is independent of the power level. ISAT is necessary to maintain the dimmer TRIAC in the conduction mode.
AN368 4.3 Completing the Design Step 12) Choose Power Components The maximum drain current through transistor Q4 is limited to 297.5mA. The smallest 400V MOSFET in a package capable of handling the power is 1A. The flyback stage output diode D15 has a peak current of (5.57 0.2975) = 1.66A, an average DC current of 488mA, and a max reverse voltage of 250V/5.57+32V = 77V. A 1A 90V Schottky diode meets the requirements. The boost diode D1 has a peak current of 0.6A and an average DC current of 7.3W/200V = 36.
AN368 Design Tip - Sense resistor is open circuited or unusually large Check: Determine if the power supply is operating in either auto-restart or latch mode when load is open and output voltage reaches the threshold. Test Stimulus: Connect a resistor with a high impedance in series with the original current-sensing resistor, and then connect a switch in parallel with the high-resistance resistor. Manually switch on/off. The CS voltage should rise to above 1.
AN368 Design Tip - Prevent output current from exceeding VOVP(th) if one channel is open circuited Check: Determine if the power supply is operating in either auto-restart or latch mode when load is open and output voltage reaches the threshold. The comparator threshold is set to 1.25V, which should translate to a particular voltage level on the primary side. Test Stimulus: Unplug one or both of the loads.
AN368 j. External Overtemperature Protection The external negative temperature coefficient (NTC) thermistor reference is a Murata NCP18WF104J03RB. This NTC is 100k with a Beta of 4275. If the temperature exceeds 95°C, RNTC is approximately 6.3k and resistor R29 is 14k, so the eOTP pin has a total resistance of 20.3k. Solving Equation 75 for CODETEMPeOTP: 4M 4M CODE TEMPeOTP = -------------------------------- = ------------------------------------------ = 197 [Eq.142] R NTC + R S 6.
AN368 Step 17) Designing the EMI Filter Limitations are imposed on the values of the inductance, capacitance, and resistance assigned to the EMI components in an effort suppress ringing that may be excited by the dimmer turn on and the boost stage conduction. The value selected for inductors L1 and L2 was 3.3mH, and the value selected for resistors R1 and R8 was 2k. The value for capacitor C4 was selected to be a 4700pF and C1 was selected to be a 0.1F. a.
AN368 5 Appendix 5.
AN368 Add Name 19 P12_MSB 20 P12_LSB 7 6 5 4 3 2 1 0 -(23) 22 21 20 2-1 2-2 2-3 2-4 0 0 0 0 0 0 0 0 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 1 1 0 1 1 0 1 0 -(2 ) 2 2 2 1 2 0 -1 -2 -3 1 1 1 1 0 1 0 0 -5 -6 -7 -8 -9 -10 -11 -12 3 21 22 P11_MSB P11_LSB 2 2 0 3 23 24 25 26 27 P00_MSB P00_LSB Q3_MSB Q3_LSB Q2_MSB -(2 ) 29 30 31 Q2_LSB Q1_MSB Q1_LSB Q0_MSB 33 Q0_LSB GD_DUR 35 36 37 38 Config2 Config3 Config4 S2DI
AN368 Add Name 39 Config7 40 41 42 43 44 45 46 7 48 1 CH1CUR 1 1 Config12 PID TTRFREQ Config15 Config16 Config17 50 Config18 PEAK_CUR 3 1 1 RSHIFT[3:0] 2 1 0 - - - 0 1 0 CH1CURMS B CH1_ZCD[2:0] 1 1 0 0 1 1 0 0 27 26 25 24 23 22 21 20 1 1 1 1 1 1 1 0 BUCK[3:0] Config10 CH2CUR 4 PRCNT[3:0] Config8 49 51 5 PROBE CH2CURMS B REI_ZCD[2:0] 0 0 0 0 0 0 0 0 27 26 25 24 23 22 21 20 0 1 1 1 1 1 1 1 - - - TIMEOUT[1:0]
AN368 Add Name 7 6 5 4 3 2 1 0 66 Reserved 0 1 0 1 0 0 0 0 67 Reserved 1 0 0 1 0 1 0 0 68 Reserved 0 0 0 1 0 0 0 1 69 Reserved 1 0 0 0 1 1 1 0 - - - - - - - CRC 70 Config38 1 0 0 0 1 0 1 1 71 Reserved 0 1 1 0 1 1 0 0 72 Reserved 0 0 1 1 1 0 1 1 73 Reserved 0 1 0 1 1 0 1 0 74 Reserved 0 0 1 1 0 1 0 0 75 Reserved 1 0 0 1 0 1 0 - - - - - - 1 0 0 0 1 1 1 1 - - - - - - VDIFF_LA
AN368 Add Name 91 Config59 92 Config60 7 6 5 4 3 2 eOTP[4:0] 1 1 1 - PLC - 1 0 1 DITNODIM DITLEVEL[1:0] 1 0 HI_SAT[2:0] 1 0 1 CS_DELAY[2:0] 0 0 - - 1 1 1 1 1 DITCHAN - - - - 0 1 0 1 1 93 Config61 94 Config62 1 1 1 1 0 1 0 1 95 Reserved 0 0 0 0 0 0 0 1 96 Reserved 0 0 0 0 0 0 0 0 97 Reserved 0 0 0 0 0 0 0 0 98 Reserved 0 0 0 0 0 0 0 0 99 Reserved 0 0 0 0 0 0 0 0 100 Reserved 0 0 0 0 0 0 0 0
AN368 Add Name 123 CH2_CAL3B 124 CRC_MTAG3B 125 126 CH1_CAL3C CH2_CAL3C 127 CRC_MTAG3C 7 6 - - 0 0 0 0 0 27 26 25 24 23 0 0 0 0 0 SET_3C - 0 0 - - 0 0 2 7 0 AN368REV2 2 6 0 5 4 3 2 1 0 0 0 0 22 21 20 0 0 0 0 0 0 0 CH2_CAL3B[5:0] CH1_CAL3C[5:0] 0 0 0 0 CH2_CAL3C[5:0] 0 2 5 0 0 2 4 0 0 2 3 0 0 2 2 0 2 1 0 20 0 75
5.2 Schematic Figure 23.
AN368REV2 5.3 Dimensions 1.310 " 0.485 " R11 C23 C20 TX1 Q 2 R9 L1 C6 FH 1 L J7 C1 C4 Q1 C13 1.025 " J 12 0.425 " 4 J1 0.625 " C11 R+ N J9 RJ 13 L2 J8 L3 C15 Q5 NTC+ C8 W+ W- 2.050 " Figure 24.
5.4 Bill of Materials Item Designator 1 2 5 6,8 9-10 11 12 13 14 17 18 19 22 23 24-26 27 28 29 30 31 32 33-34 35 Value Manufacturer Part Number Package Per Qty Assembly Notes BR1 HD04 Diodes, Inc. RH04-T 4 pin Mini- Dip 1 C1 CAPACITOR PEN FILM, 0.1UF, 250V, RADIAL Epcos B32559C3104K alt C050-035X075 1 5.50 x 3.50 C0402 5.50 x 3.50 C0603 10X16 1210 E2.5-5 C0603 C0603 E2.5-5 C0805K C050-035X075 C0603 E2.
Item Designator Value 42-43 44 45 46-47 48-49 50-53 54-56 57 58 COILCRAFT 3.3mH Drum Inductor E13/6/6 MOSFET N-CH 450V 1.5A IPAK MOSFET N-CH 500V 380MA TO-92 MOSFET N-CH 60V 1.2A SOT23-3 MOSFET N-CH 60V 200MA SOT23-3 MOSFET N-CH 600V 1A IPAK RES 2.00K OHM 1/10W 1% 0603 SMD RES 10.0K OHM 1/10W 1% 0402 SMD RES 6.81K OHM 1/10W 1% 0402 SMD RES 47K OHM 1/10W 1% 0402 SMD RES 47 OHM 1/10W 5% 0402 SMD RES 22.0K OHM 1/10W 1% 0603 SMD RES 4.
AN368 Revision History 80 Revision Date Changes REV1 SEP 2012 Initial Release.
