AN333 CS470xx Firmware User’s Manual: General Overview and Common Firmware Modules Contents Overview Document Strategy This document provides a description of the operation of firmware for the CS470xx family of DSPs and attempts to explain frequently used terminology and, at the same time, systematically explains the OS operation and communication for the CS470xx.
1 Document Strategy 1 Document Strategy The CS470xx has been designed with inherently flexibility in terms of firmware usage. Each instance of operation of the CS470xx can potentially use a different mix of DSP firmware, depending on the needs of the end user. The strategy adopted to document the various DSP firmware is based on a single general overview firmware user’s manual coupled with an individual application note for each DSP firmware module offered by Cirrus Logic.
2 Overview 2 Overview The firmware that runs on this device expects a stereo or multichannel PCM input source. This section describes the overlays. The DSP program memory is divided into five functional segments called overlays that can be thought of as the locations for the firmware modules that are accessed and implemented by the DSP. Firmware modules are downloaded into their respective overlays either from internal ROM, or from the host. • OS Overlay Manages the overall operation of the DSP.
2.2 Download Sequence Step 1: Download the firmware OS _p*_**.uld Automatically fills the OS overlay. (*2, 4, 6, or 8 for memory map ; **device and version) Step 2 (optional ): Download a matrix processing module (Examples: Crossbar Mixer, Pro Logic IIx, DTS Neo:6®) Automatically fills the matrix processing overlay. Step 3 (optional): Download a virtual processing module (Examples: Dolby Headphone, Dolby Virtual Speaker™) Automatically fills the virtual processing overlay.
AN333 2.3 Firmware Modules and Associated Application Notes Table 2-1.
Table 2-1. Firmware Module Read and Write Addresses with Associated Application Note Reference (Cont.
Table 2-1. Firmware Module Read and Write Addresses with Associated Application Note Reference (Cont.) DSP Firmware Module / (Application Note Name) Supported Memory Map(s) (Firmware Version) Write Request Read Request Read Response Post-processing Overlays (continued) SPP (Standard Post Processing) in DSP Composer Module Processing Order: 1. Tone Control 2. BM 3. Delay 4. AM See individual module application notes. APP (Advanced Post Processing) in DSP Composer Module Processing Order: 1.
3 Firmware Messaging 3 Firmware Messaging While using the CS470xx, it is necessary to communicate with the DSP in order to control or monitor the various downloaded firmware modules. We refer to this process of communication as firmware messaging. The purpose of this section is to describe the types and formats of these firmware messages.
3.1 Communication Overview Fig. 3-2 provides the format of a solicited read message: Read Command Word: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OPCODE[31:16] (Bits 31:24 = Module ID+0x80, bits 23:20 = 0xc, bits 19:16 = ) 8 7 6 5 4 3 2 1 0 2 1 0 2 1 0 INDEX[15:0] (First index to be read) Figure 3-2. Read Command Data Word Fig.
4 Operating System (OS) Firmware Module 4 Operating System (OS) Firmware Module Unsolicited Read Command Word: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OPCODE[31:16] 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 INDEX[15:0] Unsolicited Read Data Word: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 DATA WORD[31:0] Figure 4-1. Unsolicited Read Command and Data Words Table 4-1 describes the API used to control the OS firmware module.
4 Operating System (OS) Firmware Module Table 4-1. OS Firmware Manager Index 0x0000 Variable KICKSTART 0x0001 0x0002 IO_CONFIG OUTPUT_MODE_CONTROL† AN333 Description Bit 16: 0/1 Disable/enable malloc failure reporting. Bit 13: 0/1 Disable/enable continual GPIO updating. Only applicable if Bit 12 is set. If Bit 12 is disabled, audio pins are be available. Bit 12: 0/1 Disable/enable GPIO updates. Bit 9: 0/1 Disable/enable hardware watchdog timer reload. Bit 8: 0/1 Disable/enable hardware watchdog timer.
4 Operating System (OS) Firmware Module Table 4-1. OS Firmware Manager (Cont.) Index 0x0003 Variable SAMPLE_RATE† 0x0004–0x0008 0x0009 Reserved SOFTBOOT† 0x000A WATCHDOG_CONFIG1 0x000B TIMER0_RELOAD_COUNT1 0x000C TIMER_MODULE_COUNT1 0x000D–0x003A 0x003B Reserved GPIO_D† 12 Description The host must set the sample rate variable to inform firmware modules of the sample rate. Some firmware modules use this information to calculate correct coefficients or use the correct table data.
4 Operating System (OS) Firmware Module Table 4-1. OS Firmware Manager (Cont.) Index 0x003C Variable GPIO_OE 0x003D GPIO_MUX 0x003E–0x0043 0x0044 Reserved PLL_STANDARD_CONFIG 0x0045 PLL_CUSTOM_CONFIG0 0x0046 PLL_CUSTOM_CONFIG1 0x0047–0x004E 0x004F Reserved SW_NUM_CHANS 0x0050–0x0054 0x0055 Reserved MALLOC_SUCCESS_AND_ ATTEMPT_COUNTS 0x0056–0x0058 Reserved AN333 Description GPIO data direction register. Bits 31:0 When Bit[i] is 1, pin GPIO[i] is configured as an output.
4 Operating System (OS) Firmware Module Table 4-1. OS Firmware Manager (Cont.
4 Operating System (OS) Firmware Module Table 4-1. OS Firmware Manager (Cont.) Index 0x0071 0x0074 0x0075 0x0076 0x0077 0x0078 0x007E Variable OUTPUT_APBSRC_FSI_SEL Description Bits 31:1 Reserved Bit 0 FSI Select: 0x0 - FSI = SPDIFRX_LRCLK 0x1 - FSI = DAI1_LRCLK 1. When output APBSRC is enabled, it must be ensured that DACSRC_FSI_SEL and OUTPUT_APBSRC_FSI_SEL is the same which could come from either DAI_LRCLK or SPDIFRX_LRCLK. 2.
4.1 Memory Configurations for IO_CONFIG (Index 0x0001) 4.1 Memory Configurations for IO_CONFIG (Index 0x0001) Table 4-2 shows the memory configurations for IO_CONFIG. Table 4-2. Memory Configurations for IO_CONFIG (Index 0x0001) Firmware Version V01 V03 V05 V07 V09 V11 V13 Memory Configurations P10 P12 P10 P12 — — — — — P12 P10 — — P12 P8 P8 — P8 — — — P14 P14 P14 — — — — 4.2 Details of Index 0x0001 Table 4-3.
4.2 Details of Index 0x0001 Table 4-5.
4.2 Details of Index 0x0001 Table 4-5. Input Configurations versus Slot index for Setting Up Input Channel Remap (Cont.
4.3 OS Manager in DSP Composer 4.3 OS Manager in DSP Composer Most configuration information described in Section 4 can be controlled in DSP Composer. The OS Manager indices are available in the Audio In, Audio Out, and System blocks. To insert these, simply drag the Audio In, Audio Out, and System blocks to the workspace. When the Audio In, Audio Out, and System blocks are on the workspace, the pre-kick and runtime controls are accessible by double-clicking in the corresponding blocks.
4.4 Unsolicited Messages 4.4 Unsolicited Messages Index = 0xHHHH, data value = 0xhhhhhhhh No Write Message. No Read Request. Unsolicited Read Response = 0x8100HHHH 0xhhhhhhhh Table 4-6. Unsolicited Messages Index 0x0000 Message MALLOC_FAILURE 0x0002 PLL_OUT_OF_LOCK 4.4.1 Description Bits 19:16 1 = MALLOC_ERROR_REQ_LIST_OVERFLOW—too many requests.
4.4 Unsolicited Messages Table 4-7. Autodetect Messages Index 0x0000 AN333 Variable AUTODETECT_RESPONSE Description Bit 31 = Decodable_Stream_Flag= 0/1 = This stream is not/is decodable by the application (no need for new download if 1). Bit 5 Non_IEC61937_Stream_Flag= 1/0 = This stream is not/is IEC61937 compressed data. If Non_IEC61937_Stream_Flag=1 Bits [4:0] = Non_IEC61937 Stream Descriptor. 0x00 = Silent Input Data (Out of Application Sync). 0x01 = DTS Format-16 elementary stream.
5 Audio Manager Firmware Module 5 Audio Manager Firmware Module The Audio Manager Firmware module provides the ability for the microcontroller to easily manage general audio controls such as gain, mute, trim and channel remap. Index = 0xHHHH, data value = 0xhhhhhhhh Write = 0x8300HHHH 0xhhhhhhhh Read Request = 0x83c0HHHH; Read Response = 0x03c0HHHH 0xhhhhhhhh Table 5-1.
5 Audio Manager Firmware Module Table 5-1. Audio Manager (Cont.
5.1 Audio Manager in DSP Composer Environment Table 5-1. Audio Manager (Cont.) Index 0x0020 Variable DAO2_XMT_LEFT_REMAP† or DAC1_DATA3_L_REMAP 0x0021 DAO2_XMT_RIGHT_REMAP† or DAC1_DATA3_R_REMAP 0x0022 CONTROL_WORD† Description Selects which internal channel (0-15) is routed to DAC1 channel 6 and DAO2 XMT LEFT (if DAO2 XMT is enabled). Note: In case DAO XMT2 is enabled, this remap will supersede the remap definition DAO1_DATA2_L_REMAP. A single internal channel may be mapped to multiple outputs.
6 PCM Firmware Module 6 PCM Firmware Module The PCM firmware module provides routing and control functions for stereo and multichannel PCM input. The PCM firmware is co-resident with the OS module. There are two main modes of PCM operation, stereo and multichannel. 6.1 PCM Manager Index = 0xHHHH, data value = 0xhhhhhhhh Write = 0x9B00HHHH 0xhhhhhhhh Read Request = 0x9BC0HHHH; Read Response = 0x1BC0HHHH 0xhhhhhhhh Table 6-1.
6.2 PCM Manager in DSP Composer Table 6-1. PCM Manager (Cont.
6.3 PCM Module Notes 6.3 PCM Module Notes The following are the possible PCM input modes: • Stereo Mode: Stereo PCM into DAI_D4. 2 Channel Mode set in IO_CONFIG in the OS Manager. • Multichannel Mode: PCM into DAI_D0–DAI_D3. Multichannel Mode set in IO_CONFIG in the OS Manager. Stereo and Multichannel input modes above are mutually exclusive and must be configured prior to runtime (pre-kick-start). At runtime, switching between modes is not allowed.
8 Document Revisions 8 Document Revisions Revision Date Changes RC12 February, 2012 Updated description of 0x0045 and 0x0046 in Table 4-1. Updated variable and description of 0x005D–0x0060 in Table 4-1. RC13 July, 2012 Marked 0x003B and 0x0074–0x0077 as runtime configurable, listed 0x0055 and 0x0078 as read only, and updated description of 0x0078 in Table 4-1. Added Fig. 4-2 to show autodetect/autoswitch controls. Updated footnotes in Table 4-3.
