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CS556x / 7x / 8x:

Converting Output Data from Serial to Parallel

1. Introduction

The CS556X, CS557X, an d CS558X series of high-throu ghput Delta-Sigma A/D co nverters output data in serial for-

mat. Some applications may require that data be available in parallel format. This application note will discuss how

to use common serial-to-parallel register ICs to provide parallel data output capability for these A/D converters.

Some A/D conver ters provide parallel output data as an output option. While this makes for faster data transfer it

can introduc e some possible comprom ises in the performan ce of the A/D converte r. A parallel interface re quires

many more pins on the A/D than a serial interfac e. This factor can increase the cost, but a larger concern should

be how a parallel inter face can reduce perfor mance. The data interface has m any more connections via bond wires

to the semiconductor die. When the digital data on the digital bus is changing each bond wire acts as a radiator of

an electromagnetic field. This electromagnetic field can interfere with the performance of th e converter. The digita l

activity on the bus need not be due to the converter itself but may be caused by other peripherals using the same

bus. Many A/D converters that have parallel inter faces recommend that bus activity be stopped when a conversion

is performed, and that the data from the converter be read when the converter is not performing a conversion. An-

other option would be to provide a second set of latches outside the A/D to isolate the bus activity from being on the

digital output pins of the converter itself.

2. The CS556x/7x/8x

Cirrus Logic has chosen to offer the CS556X/7X/8X series of converters with only a serial interface. This reduces

the package pin count and also reduce s the number of digita l interface pins that can radiate noise onto the converter

die. The serial in te rface pr ovides two different modes of operatio n. The serial port on the converter can op erate in

either master mode, where the converter itself outputs the data according to its own timing (this mode is called the

SSC mode, synchronous self-clock mode). The second mode is where the serial port acts as a slave device to an

external controller, where the serial data is output from the port according to the clock provided by the external de-

vice (this mode is the SEC mode, synchronous external clock mode).

3. Serial-to-Parallel Conversion

If an application requires a parallel interface to read the converter data, then the A/D can be configured in the SSC

serial port mode and directly interfaced to serial-to-parallel registers. Figure 1 illustrates the CS556x/7x/8x A/D con-

verter interfaced to a set of 74VHC595 serial-to-parallel registers. The SMODE pin of the converter is tied to the

VL supply (tied high) to set the serial port mode of the converter into the SSC (master) mode. At the end of each

conversion th e RDY

output from the converter will transition low, and the SCLK and the SDO outputs will become

active. The data bits from SDO will be shifted into the first 74VHC595 register by the rising edges of SCLK. The

74VHC595 device holds eight bits of data. Multiple 74HVC595 devices are daisy-chained to provide either a 16-

bit parallel (two 74VHC595s) or a 24-bit parallel (three 74VHC595s) inter face. The 74VHC595 has a tri- state output

so the outputs of these devices can be attached to a multi-periphe ral bus. The RDY

signal will return high when all

the bits from the converter have been shifted into the registers. When RDY

transitions high it will set the NC75Z175

latch to provide a "data re ady" signal at its Q output. When the read signal from the system goes low, the outputs

of the 74VHC595 devices will come out of tri-state and place their data on the bus. The falling read signal will also

clear the "data ready" signal back to a zero at the Q output of the NC75Z175 latch.

AN313

JUN ‘07

AN311REV1

Summary of content (4 pages)

PAGE 1
AN313 CS556x / 7x / 8x: Converting Output Data from Serial to Parallel 1. Introduction The CS556X, CS557X, and CS558X series of high-throughput Delta-Sigma A/D converters output data in serial format. Some applications may require that data be available in parallel format. This application note will discuss how to use common serial-to-parallel register ICs to provide parallel data output capability for these A/D converters. Some A/D converters provide parallel output data as an output option.
PAGE 2
AN313 VL PWR RST DOUT QH 74VHC595 QG QF LATCH CLK QE QD SHIFT CLK QC QB DIN QA GND D23 D22 D21 D20 D19 D18 D17 D16 OE 24-Bit Data 16-Bit Data VL PWR DOUT RST QH 74VHC595 QG QF LATCH CLK QE QD SHIFT CLK QC QB QA DIN GND D15 D14 D13 D12 D11 D10 D9 D8 OE VL VL PWR RST QH DOUT 74VHC595 VL SMODE CS556x CS557x CS558x SCLK QG QF LATCH CLK QE QD SHIFT CLK QC QB SDO QA DIN GND D7 D6 D5 D4 D3 D2 D1 D0 OE RDY CONV VLR VL PWR NC75Z175 Q D CL Data Ready C GND Read
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AN313 Figure 2 shows the timing of the RDY/, SCLK, and SDO signals from the A/D converter. RDY SCLK(o) SDO MSB MSB–1 LSB+1 LSB Figure 2. CS556x/7x/8x Serial Data Output Signals 4. Minimizing EMI There are applications where output data from a converter must pass via a cable to another circuit board assembly. If this is required, each active signal should have its own ground wire “partner”. On a connecter, such as a dual row stake header, each active signal should be paired with a ground signal.
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AN313 Revision History Release Date REV1 JUN 2007 Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.