User guide

AN312REV2 3
AN312
3.1 CobraNet Clock Modes
This section describes each of the CobraNet clock modes.
3.1.1 0x00 Mode - Internal Mode (Default)
The 0x00 Mode is the default clock mode of a CobraNet interface. When operating in this mode:
As Conductor: The master audio clock (MCLK) is generated by the VXCO parked at its center fre-
quency. Word clock (FS1) and bit clock (SCLK) are derived directly from MCLK.
As Performer: The master audio clock (MCLK) is generated by the VXCO, which receives frequency
adjustments from the beat packets received from the Conductor node over the network interface, in-
suring that the Performer's clock is in sync with the Conductor. Word clock (FS1) and bit clock (SCLK)
are derived from MCLK.
Figure 3. 0x00 Mode Typical Connections
Figure 4. Clock Circuit as Used by 0x00 Mode with CM-1 Module
CobraNet Interface
F
S
1
(
L
R
c
l
o
c
k
)
SCLK
(Bit clock)
MCLK_OUT
(Master Audio
Clock)
DAC or ADC
Beat Received
VCXO
24.576MHz
+/- 100 PPM
DAC
MCLK_IN
MCLK_SEL
REFCLK_Enable
REFCLK_Polarity
REFCLK
Edge
Detect
MCLK
MUX
Beat
MUX
Phase
Detector
Sample
Phase
Counter
RST
Loop
Filter
control
Clock
Out
MCLK_OUT (master)
FS1 (word)
SCK (bit)
Audio
Clock
Generator
Clock Config
Signal
Path
Control
Path
Hardware FPGA Software
Active
Signal
Path