User guide

10 AN312REV2
AN312
Figure 16. 0x14 Mode Typical Connection
(Master and Reference Clock Supplied to Slave Interfaces within Same Chassis when Using CM-1)
Figure 17. Clock Circuit as Used by Mode 0x14 with CM-1 Module
FS1
(LR clock)
SCLK
(Bit clock)
CobraNet Interface
(Slave)
Mode 0x14
FS1
(LR clock)
SCLK
(Bit clock)
MCLK_IN
REFCLK
CobraNet Interface
(Slave)
Mode 0x14
FS1
(LR clock)
SCLK
(Bit clock)
MCLK_IN
MCLK_OUT
24.576 MHz
REFCLK
FS1
CobraNet
Interface
(Master)
Typically Mode
0x00
Beat Received
VCXO
24.576MHz
+/- 100 PPM
DAC
MCLK_IN
MCLK_SEL
REFCLK_Enable
REFCLK_Polarity
REFCLK
Edge
Detect
MCLK
MUX
Beat
MUX
Phase
Detector
Sample
Phase
Counter
RST
Loop
Filter
control
Clock
Out
MCLK_OUT (master)
FS1 (word)
SCK (bit)
Audio
Clock
Generator
Clock Config
Signal
Path
Control
Path
Hardware FPGA Software
Active
Signal
Path