AN298 CS485xx Firmware User’s Manual: General Overview and Common Firmware Modules Contents Overview Document Strategy AN298 provides a description of the operation of firmware for the CS485xx family of DSPs. This document gives a general overview to the family of CS485xx Firmware User’s Manuals designated by the general name AN298[X][Y]; where [X] = MPM (Matrix Processing Module), VPM (Virtual Processing Module), PPM (Post Processing Module), and [Y] = A,B,C, etc.
1 Document Strategy 1 Document Strategy The CS485xx has been designed with an inherent flexibility in terms of firmware usage. Each instance of operation of the CS485xx can potentially use a different mix of DSP firmware depending on the need of the end user. As such, the strategy adopted to document the various DSP firmware is based on a single General Overview coupled with an individual Firmware User’s Manual for each DSP firmware module offered by Cirrus Logic.
2 Overview 2 Overview The firmware that runs on this device expects a stereo or multi-channel PCM input source. This section describes the different overlays as well as the functionality of the various processor module overlays. Mid-Processor Module PCM inputs Downsampler Virtualizer-Processor Module Mid-Processor Overlay e.g. PLII, PLIIx, Neo6, Crossbar, Viva+, COMS2, Neural Surround, Circle Surround 2 e.g.
2.2 Code Image (.uld) Files 2.2 Code Image (.uld) Files Each overlay is a separate code image file (.uld) that is loaded individually into the DSP. To change the functionality of the application, only the overlay of interest needs to be loaded. For example the Post Processing overlay can be exchanged from SPP to APP by reloading only the Post Processing overlay. This reduces the system response time to user changes as well as the code image storage requirements.
2.3 Download Sequence This variable is the specific memory map for the various overlays and can be specific to a particular version of ROM Current Firmware versions are: • • • • • • • • • 01 = CS485xx 02 =CS48DV2A 03 = CS48DV2B 04 = CS485xx 05 = CS485xx 06 = CS48AU2B 09 = CS485xx EE = This variable indicates a major revision, increments when rc99 -> rc1 FF = This Variable indicates a minor revision, increments by one for each new .uld build 2.2.1.2 Example of .uld file name An example of a .
2.3 Download Sequence Step 1: Download the firmware OS_p*_**.uld Automatically fills the OS Overlay. (*2, 4, 6, or 8 for memory map; **device and version) Step 2 (optional): Download a matrix processing module virtual processing module (e.g. Crossbar Mixer, Pro Logic IIx, DTS Neo6 etc.) Automatically fills the Matrix Processing Overlay. Step 3 (optional): Download a (e.g. Dolby Headphone, Dolby Virtual Speaker etc.) Automatically fills the Virtual Processing Overlay.
AN298RC14 2.4 Firmware Modules and Associated Application Notes Table 2-1. Firmware Module Read and Write Addresses with Associated Application Note Reference DSP Firmware Module / (Application Note Name) Firmware Version/Memory Map(s) Supported Write Request Read Request Read Response See Table 2-2 for a list of Firmware versions/ memory maps associated with the various CS48xxx products.
AN298RC14 Table 2-1. Firmware Module Read and Write Addresses with Associated Application Note Reference (Cont.
AN298RC14 Table 2-1. Firmware Module Read and Write Addresses with Associated Application Note Reference (Cont.
AN298RC14 Table 2-1. Firmware Module Read and Write Addresses with Associated Application Note Reference (Cont.) DSP Firmware Module / (Application Note Name) Firmware Version/Memory Map(s) Supported Write Request Read Request Read Response Audyssey Adaptive Bass eXtension (ABX) Module (ANPPMT) V06 0xC900HHHH 0xhhhhhhhh 0xC9CNHHHH 0x49C0HHHH 0xhhhhhhhh SPP (Standard Post Processing) in DSP Composer Module Processing Order: 1. Tone Control 2. BM 3. Delay 4.
2.4 Firmware Modules and Associated Application Notes Table 2-2.
3 Firmware Messaging 3 Firmware Messaging While using the CS485xx, it is necessary to communicate with the DSP in order to control or monitor the various downloaded firmware modules. We refer to this process of communication firmware messaging. The purpose of this section is to cover the types and formats of these firmware messages.
3.
4 Operating System (OS) Firmware Module 4 Operating System (OS) Firmware Module Indices of the Firmware Module can differ in properties that are important to the system firmware programmer. Indices marked by a ‘†’ can be modified after kick-starting the application. However, indices not marked by a ‘†’ must be configured by the system host controller before the kick-start message is sent to begin decoding.
4.2 OS Manager Table 4-1. OS Module API Index 0x0000 Variable KICKSTART 0x0001 IO_CONFIG 0x0002 OUTPUT_MODE_CONTROL† AN298RC14 Description Bit 22: 0/1 Disable/Enable unsolicited message on sampling frequency change detection. It is strongly recommended that both Bit 21 and Bit 22 be enabled or both be cleared/disabled. Bit 22 is only available on CS48AU2B, CS48DV2B, and CS48DV6B DSPs. Bit 21: 0/1 Disable/Enable continual check and re-evaluation of sampling frequency.
4.2 OS Manager Table 4-1. OS Module API (Cont.) Index 0x0003 Variable SAMPLE_RATE† 0x0004–0x0008 0x0009 Reserved SOFTBOOT† 0x000A–0x003A 0x003B Reserved GPIO_D 0x003C GPIO_OE 0x003D GPIO_MUX 0x003E–0x0043 Reserved 16 Description Set by host Bits 3:0 Sample Rate 0x0 = 48 kHz 0x1 = 44.1 kHz 0x2 = 32 kHz 0x3 = 0x4 = 96 kHz 0x5 = 88.2 kHz 0x6 = 64 kHz 0x7 = 0x8 = 24 kHz 0x9 = 22.05 kHz 0xA = 16 kHz 0xB = 0xC = 192 kHz 0xD = 176.
4.3 OS Manager in DSP Composer Table 4-1. OS Module API (Cont.) Index 0x0044 Variable PLL_STANDARD_CONFIG 0x0045 PLL_CUSTOM_CONFIG0 0x0046 PLL_CUSTOM_CONFIG1 0x0047–0x0051 0x0052 Reserved ZERO_LSB_MASK 0x0053–0x0054 0x0055 Reserved MALLOC_SUCCESS_AND_ ATTEMPT_COUNTS Reserved 0x0056 Description Bits 11:4 Reference Clock Frequency - Frequency of clock attached to XTI pin, must be set: 0x00 = 12.288 MHz 0x01 = 24.576 MHz 0x02–0x0F = Reserved 0x10 = 18.
4.4 Unsolicited Messages Table 4-2. Unsolicited Messages Index Message Description 0x0000 MALLOC_FAILURE Bits 19:16 1 = MALLOC_ERROR_REQ_LIST_OVERFLOW—too many requests. 2 = MALLOC_ERROR_NO_FREE_BLOCK— no non-modulo free block was available to service next request) 3 = MALLOC_ERROR_NO_MOD_FREE_BLOCK—no modulo free block was available to service next request) 0x0002 PLL_OUT_OF_LOCK 18 Bit 23 = 1. Bits 22:0 = Reserved.
5 Audio Manager Firmware Module 5 Audio Manager Firmware Module 5.1 Overview The Audio Manager Firmware module provides the ability for the microcontroller to easily manage general audio controls such as gain, mute, trim and channel remap. 5.2 Audio Manager Index = 0xHHHH, data value = 0xhhhhhhhh Write = 0x8300HHHH 0xhhhhhhhh Read Request = 0x83c0HHHH Read Response = 0x03c0HHHH 0xhhhhhhhh Table 5-1. Audio Manager Index Variable Description 0x0000 GAIN† 0x00000000–0x7FFFFFFF (-inf. to +24 dB).
5.2 Audio Manager Table 5-1. Audio Manager (Cont.) Index Variable 0x000D Reserved 0x000E CHAN_8_TRIM† 0x00000000–0x80000000 (0.0 to 1.0) Volume trim for channel 8 (Left Downmix Channel) Default = 0x80000000 0x000F CHAN_9_TRIM† 0x00000000–0x80000000 (0.0 to 1.0) Volume trim for channel 9 (Right Downmix Channel) Default = 0x80000000 0x0010 CHAN_10_TRIM† 0x00000000–0x80000000 (0.0 to 1.
5.3 Audio Manager in DSP Composer Environment Table 5-1. Audio Manager (Cont.) Index Variable Description 0x001F Reserved 0x0020 DAO2_DATA1_L_REMAP*** Selects which internal channel (0-11) is routed to DAO2 channel 2. A single internal channel may be mapped to multiple outputs. Default = 0x0000000e (Left Auxiliary Channel Audio Data) 0x0021 DAO2_DATA1_R_REMAP*** Selects which internal channel (0-11) is routed to DAO2 channel 3. A single internal channel may be mapped to multiple outputs.
5.4 DSP Composer Sample Projects 5.4 DSP Composer Sample Projects Sample projects for various firmware applications have been provided in DSP Composer. Go to File > Open and browse to CirrusDSP\CS485xx\projects\. There are several sample projects that exercise other modules. Open ‘pcm_spp.cpa’. This project is configured for PCM processing, as shown in Fig. 5-4. Figure 5-4.
6 PCM Firmware Module 6 PCM Firmware Module 6.1 Overview The PCM firmware module provides routing and control functions for stereo and multi-channel PCM input. The PCM firmware is co-resident with the OS module. There are two main modes of PCM operation, stereo and multi-channel. 6.2 PCM Manager Index = 0xHHHH, data value = 0xhhhhhhhh Write = 0x9B00HHHH 0xhhhhhhhh Read Request = 0x9BC0HHHH Read Response = 0x1BC0HHHH 0xhhhhhhhh Table 6-1.
6.2 PCM Manager Table 6-1. PCM Manager (Cont.
6.3 PCM Manager in DSP Composer 6.3 PCM Manager in DSP Composer All configuration information described in Section 6.2 can be controlled in DSP Composer. Note that IO Buffer Channel availability is device specific. The PCM Manager is part of the System block. To insert System block, drag in onto the workspace. Once the System block is on the workspace the runtime and pre-kick controls for the PCM Manager can be accessed by double-clicking the System block.
6.4 PCM Module Notes Table 6-2. Valid IO_BUFF_*_SOURCE Values Value Source (multichannel mode) Source (Stereo mode) 0 DAI1_D0 Left DAI Left 1 DAI1_D0 Right DAI Right 2 DAI1_D1 Left None 3 DAI1_D1 Right None 4 DAI1_D2 Left None 5 DAI1_D2 Right None 6 DAI1_D3 Left None 7 DAI1_D3 Right None 8 DAI1_D4 Left None 9 DAI1_D4 Right None 10 DAI2_D0 Left None 11 DAI2_D0 Right None 0x08000000 None None 6.
7 Low Power Mode 7 Low Power Mode Note: The Low Power Mode section will be moving to the CS485xx Hardware User’s Manual in the next revision of that manual. The CS485xx has a low power mode to enable power savings when not in use. Low power mode is entered during the softboot procedure. 7.1 Low Power Mode Messaging One message is relevant to the low power mode procedure for the CS485xx. This message is SOFTBOOT_LP. The host must read any ACK and prior messages before low power mode may commence.
7.3 Getting Out of Low Power Mode Table 7-1. wakeup_uld 28 .uld Options Values WAKEUP_P2.ULD 08004409 00000002 00000000 b485aa01 ffffffff 437a11f5 WAKEUP_P4.ULD 08004409 00000002 00000001 b485aa01 ffffffff 437a11f4 WAKEUP_P6.ULD 08004409 00000002 00000002 b485aa01 ffffffff 437a11f3 WAKEUP_P8.
8 Watchdog Timer 8 Watchdog Timer The CS485xx has an integrated hardware watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS485xx will reset itself in the event of a temporary system failure. In standalone mode (no host MCU), the DSP will reboot from external FLASH.
9 Document Revisions 9 Document Revisions Revision Date RC1 December, 2006 Initial Release Changes RC2 September, 2007 Updated KICKSTART and PLL_STANDARD_CONFIG; added PLL_CUSTOM_CONFIG0, PLL_CUSTOM_ CONFIG1, and MALLOC_FAILURE. RC3 December, 2007 Updated Legal Notice. Removed Softboot procedure that was duplicated in Chapter 2 of the CS485xxHardware User’s Manual. RC4 July, 2008 RC5 October, 2008 Added Bits 20, 21, and 22 to the KICKSTART variable in Table 4-1.
