Owner manual
64 AN269REV1
AN269
C.2 Reference Schematic for HOSIDEN HLAM6323 in an EP93xx System
5V_D0
5V_D1
5V_D2
5V_D3
5V_FRAME
5V_M
5V_CL1
5V_CL2
5V_DOFF
GND
VEE(-20V)
1
2
Jump_M
CON2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STN 4bit B/W LCD
CON 14
R1
CONT RAST
GND
5V
GND
2B1
13
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
GND
28
GND
34
GND
39
GND
45
GND
21
GND
15
GND
10
GND
4
2DIR
24
2OE
25
1DIR
1
1OE
48
2A8
26
2A7
27
2A6
29
2A5
30
2A4
32
2A3
33
2A2
35
2A1
36
1A8
37
1A7
38
1A6
40
1A5
41
1A4
43
1A3
44
1A2
46
1A1
47
VCC
7
VCC
18
VCC
31
VCC
42
74LV164245
74LV164245
PWR_5V0
PWR_3V3
GND
GND
5V_D0
5V_D1
5V_D2
5V_D3
5V_FRAME
5V_M
5V_CL1
5V_CL2
5V_DOFF
PWR
BLANK
SP CLK
LCD17_AC
VS_CSYNC
LCD1
LCD2
LCD3
LCD4
3V
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
EP93xx_LCD
HEADER 20X2
LCD0 LCD1
LCD2 LCD3
LCD4 LCD5
LCD6 LCD7
LCD8 LCD9
LCD10 LCD11
LCD12 LCD13
LCD14 LCD15_YSCL
LCD16_XECL LCD17_AC
SP CLK
HSYNC VS_CSYNC
BLA NK
BRI GHT_1
PWR_3V3
PWR_5V0
PWR_12V
PWR_12V
GPIO1
R2_LCD
10K
R3_LCD
10K
5V
3V
12V
Some LCDs do not need
this signal .
4 Bits Mode
We connected B[0,1,2,3] to STN LCD D[0..3].
HSYNC
Figure 26. Schematic for HOSIDEN HLAM6323 in an EP93xx System
(1 Bit per Pixel, 320 x 240)