Owner manual

12 AN269REV1
AN269
The output mode “2-2/3 Pixels Per Clock” is shown in Figures 5, 6, and 7. Since this mode is rather complex, one
diagram shows data during each of the first, second, and third SPCLK outputs. In this mode, each SPCLK will clock
out 2-2/3 pixels, with 1 bit representing the Red, Green, and Blue components of the pixel.
In the first SPCLK, pixel 0’s Red, Green, and Blue components are clocked out of P[2:0]. Pixel 1’s Red, Green, and
Blue components are clocked out of P[5:3]. Note that ONLY the Blue and Green component of Pixel 2 are clocked
out of P[7:6]. The Red component of pixel 2 will be clocked out during the second SPCLK.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
0
0
1
1
1
2
2
Pixel Data Bus
Pins P[17:0]
Pixels 0, 1, and 2 (First SPCLK)
Pixel Data Most Significant Bits
(from LUT and Blink Logic)
Figure 5. 3 Bit Per Pixel Formatted as 2-2/3 Bits, First SPCLK