AN269 Using the EP93xx's Raster Engine 1. INTRODUCTION AND SCOPE The purpose of this document is to help a user understand how to connect an LCD module to the EP93xx series of embedded processors from Cirrus Logic. A wide variety of timings and output settings are available, which allows connection to many color and black-and-white LCD displays. Some timing modes will also allow connection to an external video DAC, which can be used to drive any type of display.
AN269 3. GENERATION OF THE VIDEO CLOCK, VIDCLK The internal video clock (VIDCLK), which drives the raster engine and the external pixel clock (SPCLK), is derived from PLL1, PLL2, or the external clock input. The SPCLK signal clocks data from the EP93xx into the external LCD or display. The number of pixels per SPCLK may be 1, 2, 4, 8, or 2-2/3. Conceptually, the external clock (SPCLK) is generated by dividing the VIDCLK by the appropriate clock divider. The necessary divider depends on the output mode.
AN269 /* Desired SPCLK frequency is passed in as "freq" */ int ep93xx_set_video_div(unsigned long freq) { /* pdiv, div, psel and esel are the final values of the appropriate bit settings in the VidClkDiv register. The current "guess" for pdiv and div are j-3 and k, respectively.
AN269 4. USING THE HORIZONTAL AND VERTICAL COUNTER FOR TIMINGSIGNAL GENERATION Conceptually, all timing synchronization outputs from the EP93xx are driven from a series of down counters followed by combinational logic. The input clock to these counters is the video clock signal, VIDCLK (see “Generation of the Video Clock, VIDCLK” on page 2). There are two banks of down counter/comparators - one for horizontal and one for vertical timing generation.
AN269 When the output of the horizontal down counter rolls over, it will decrement the vertical down counter at one count per horizontal line. When the count reaches 0, the vertical down counter loads the value contained in the VLinesTotal register, and continues counting down. The VCSYNC output is generated by comparing the value of the vertical down counter with the VSyncStrtStop register. If the value of the counter is in the active range (VSyncStrtStop.Start > Vertical Counter > VSyncStrtStop.
AN269 Figure 2. Offset for HSync, HActive, VSync and HCLK HSync and Blank must be raised high after the last byte of data is transferred. Find the register values for HClksTotal, HSyncStart, HSyncStop, HActiveStrt, HActiveStop, HBlankStrt, HBlankStop, HClkStrt and HClkStop. To create these timings you must perform the following calculations.
AN269 The Calculations for HClksTotal are HClksTotal = Number of Horizontal Clocks - 1 = 20 -1 = 19 The Calculations for HSyncStart are HSyncStart = HClksTotal + Offset of Sync = 19 + 0 = 19 TheCalculations for HSyncStop are HSyncStop = HClksTotal - Screen Width + Offset of Sync = 19 - 16 + 0 =3 TheCalculations for HActiveStrt are HActiveStrt = HClksTotal + Offset of HActive = 19 -1 = 18 The Calculations for HActiveStop are HActiveStop = HClksTotal - Screen Width + Offset of HActive = 19 - 16 -1 =2 The
AN269 The Calculations for HClkStrt are HClkStrt = HClkstotal - Offset of HClk = 19 - 6 = 13 The Calculations for HClkStop are HClkStop = HClksTotal - Screen Width + Offset of HClk = 19 - 16 - 6 = -3 Since -3 is not in the range of 0 and HClksTotal, add the number of Horizontal Clocks. = -3 + Number of Horizontal Clocks = -3 + 20 HClkStop = 17 The values for HSyncStart, HSyncStop, HActiveStrt, HActiveStop, HBlankStrt, HBlankStop, HClkStrt and HClkStop are shown in Figure 2.
AN269 5. GENERAL DESCRIPTION OF PIXEL OUTPUT MODES Each display type specifies the number of bits (and therefore bits per color) clocked out per SPCLK period. The EP93xx supports a variety of formats, as specified in the “Output Shift Mode Table” and “Color Mode Definition Table” in the PixelMode register (refer to the Raster Engine chapter in the EP93xx User’s Guide for these tables). Certain restrictions apply to these settings (as certain modes must be used together).
AN269 P ix e l D a ta B u s P in s P [1 7 :0 ] (from LUT and Blink Logic) Pixel Data Most Significant Bits P i x e l 0 ( F ir s t S P C L K ) P ix e l 1 (S e c o n d S P C L K ) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 Figure 3. Single 16-bit 565 Pixel Per Clock Output The output mode “Single 16-bit 565 Pixel Per Clock” is shown in Figure 3.
AN269 Pixel Data Bus Pins P[17:0] Pixel 0 (First SPCLK) Pixel 1 (Second SPCLK) Pixel Data Most Significant Bits (from LUT and Blink Logic) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 Figure 4. Single 16-bit 555 Pixel Per Clock Output The output mode “Single 16-bit 555 Pixel Per Clock” is shown in Figure 4. In this mode, each SPCLK will clock out a single pixel, with 5 bits representing the Blue component on P[5:1], Green component on P[11:7], and Red component of the pixel on P[17:13].
AN269 Pixel Data Bus Pins P[17:0] Pixel Data Most Significant Bits (from LUT and Blink Logic) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixels 0, 1, and 2 (First SPCLK) 2 2 1 1 1 0 0 0 Figure 5. 3 Bit Per Pixel Formatted as 2-2/3 Bits, First SPCLK The output mode “2-2/3 Pixels Per Clock” is shown in Figures 5, 6, and 7. Since this mode is rather complex, one diagram shows data during each of the first, second, and third SPCLK outputs.
AN269 Pixel Data Bus Pins P[17:0] Pixel Data Most Significant Bits (from LUT and Blink Logic) 1 1 7 1 6 1 5 1 4 1 3 1 2 1 0 9 8 7 6 5 4 3 2 1 0 Pixels 2, 3, 4 and 5 (Second SPCLK) 5 4 4 4 3 3 3 2 Figure 6. 3-Bit Per Pixel Formatted as 2 2/3 Bits, Second SPCLK In the second SPCLK for 2-2/3 mode, pixel 2’s Red component will be clocked out of P[0]. All of the Red, Green, and Blue components of pixel 3 are clocked out of P[3:1]. Pixel 4’s Red, Green, and Blue components are clocked out of P[6:4].
AN269 Pixel Data Bus Pins P[17:0] Pixel Data Most Significant Bits (from LUT and Blink Logic) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixels 5, 6 and 7 (Third SPCLK) 7 7 7 6 6 6 5 5 Figure 7. 3-Bits Per Pixel Formatted as 2-2/3 Bits, Third SPCLK In the third SPCLK for 2 2/3 mode, pixel 5’s Green and Red components will be clocked out of P[1:0]. All of the Red, Green, and Blue components of pixel 6 are clocked out of P[4:2]. Pixel 7’s Red, Green, and Blue components are clocked out of P[7:5].
AN269 Pixel Data Bus Pins P[17:0] Pixels 0, 1, 2 and 3 Pixel Data Most Significant Bits (from LUT and Blink Logic) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Figure 8. 4 Pixels Per Shift Clock In “4 Pixels-Per-Shift-Clock mode“, shown in Figure 8, only 1 bit (the MSB) will be available for the Blue and Green components of the pixel. The Red component will have the two MSBs available. In this mode, there are 4 pixels clocked during each SPCLK.
AN269 6. SETTING UP DISPLAY TIMING 6.1 HSYNC/VSYNC-Style Displays In displays using a HSYNC/VSYNC-style timing interface, the following control signals are commonly used for data synchronization: – DCLK - Data Input Clock. Usually one rising/falling edge occurs per pixel or set of pixel data. This is the highest frequency interface signal, and transitions occur many times during each horizontal line. – DE - Data Enable or Valid. Used to indicate valid data is currently being clocked into the display.
AN269 Single Horizontal Line Active Video tHSYNC HSYNC tHACTIVE BLANK tDCLK SPCLK DATA Back Porch Interval tHBACKPORCH Front Porch Interval tHFRONTPORCH Single Video Frame Active Video tVSYNC VCSYNC HSYNC tVACTIVE BLANK Back Porch Interval tVBACKPORCH Front Porch Interval tVFRONTPORCH Figure 9.
AN269 6.1.1 Pixel Data Clock Rate and HClkTotal/VLinesTotal The pixel clock rate VIDCLK can be determined from the total number of VIDCLK periods per line, total number of horizontal lines, and the Refresh Rate.
AN269 6.1.2 Horizontal Alignment Signals Timings for a single horizontal line can be seen in Figure 10. To determine when these signals become active, the horizontal frame timing registers HClkTotal, HSyncStrtStop, HActiveStrtStop, HBlankStrtStop and HClkStrtStop must be set. Single Horizontal Line Active Video tHSYNC HSYNC tHACTIVE BLANK tDCLK SPCLK DATA Back Porch Interval tHBACKPORCH Front Porch Interval tHFRONTPORCH Figure 10.
AN269 Single Horizontal Line Active Video tHSYNC HSYNC tHACTIVE BLANK tDCLK SPCLK DATA HSyncStop HSyncStop HSyncStart HBlankStart HActiveStart HBlankStop HActiveStop Horizontal Line Counter Value Count = HClkTotal Count = HClkTotal - 1 Count = HClkTotal - 2 Count = 0 Back Porch Interval tHBACKPORCH Front Porch Interval tHFRONTPORCH Figure 11. Horizontal Line for HSYNC/VSYNC Display with Register Timings Next we will determine the appropriate time for the HSYNC signal to become active.
AN269 The next two values of interest for a horizontal line are the times at which active data should be clocked out. These values determine when valid data is presented to the display. As can be seen from the diagram, those times are identical to the locations at which the active data/blank signal are changing (the active region or tACTIVE). The formulas below calculate HActiveStart as the start of active data and HActiveStop as the end of active data. The offset of minus one comes from Table 2.
AN269 6.1.3 Vertical Alignment Signals Timings for a single vertical frame can be seen in Figure 12. The timing of the synchronization signals is determined by the vertical frame timing registers VLinesTotal, VSyncStrtStop, VActiveStrtStop, VBlankStrtStop, and VClkStrtStop. Single Video Frame Active Video tVSYNC VCSYNC HSYNC tVACTIVE BLANK Back Porch Interval tVBACKPORCH Front Porch Interval tVFRONTPORCH Figure 12.
AN269 then counts down by 1 for each HSYNC time period, regardless of whether SPCLK/DATA is present or not. When the counter reaches 0, it is reset to VLinesTotal. Single Video Frame Active Video tVSYNC VCSYNC HSYNC tVACTIVE BLANK Vertical Line Counter Value Count = VLinesTotal Count =0 Count = VLinesTotal - 1 Count = VLinesTotal - 2 Back Porch Interval tVBACKPORCH Front Porch Interval tVFRONTPORCH Figure 13.
AN269 The next two values of interest for a frame are the point at which active data should be clocked out. These values determine when valid data is presented to the display. As can be seen from the diagram, those times are identical to the locations at which the active data/blank signal are changing.
AN269 Display Pin EP93xx Pin CP SPCLK FRM VCSYNC LOAD HSYNC Table 4. Frame Type 1 Pin Mapping A timing diagram for this type of display is shown in Figure 14. Signal and timing names are those of the corresponding EP93xx pins.
AN269 Single Horizontal Line tHSYNCH tHSYNCL HSYNC tSPCLK tHSYNCSPCLK tSPCLKHSYNC SPCLK DATA tVCHSYNC VCSYNC (Horizontal Line 1 ONLY) tHVCSYNC One SPCLK per Horizontal Pixel Single Video Frame tVCSYNC VCSYNC HSYNC SPCLK First Line Figure 14.
AN269 6.2.1 VIDCLK and Pixel Data Clock Rate For Frame Type 1 data displays, the SPCLK will be gated such that clock pulses only occur during valid data, one pulse per data set. Note that the number of pixels per SPCLK may be 1, 2, 2-2/3, 4, or 8. Also, the number of VIDCLK periods per SPCLK may not always be constant. For example, in 2 2/3 mode, there are 3, 2, and then 3 VIDCLKs per SPCLK (thus an average of (3+2+3 VIDCLKs/SPCLK) with (2-2/3 pixels/SPCLK) = 1 VIDCLK/pixel).
AN269 Note that the number of available video clocks can also be derived by adding up the number of clocks in each region, but this approach will guarantee a more accurate line frequency. The value of NumVideoClocks will be the total number of “available” VIDCLK periods for each region of time in the horizontal line. In order to visualize this quantity, see Figure 15. Note that the NumVideoClocks quantity represents the total number of VIDCLKs per horizontal line, and therefore will be HClksTotal+1.
AN269 . Single Horizontal Line tHSYNCH tHSYNCL HSYNC tSPCLK tSPCLKHSYNC tHSYNCSPCLK SPCLK DATA tVCHSYNC VCSYNC (Horizontal Line 1 ONLY) tHVCSYNC HSyncStart HSyncStop HActiveStart HActiveStop Horizontal Line Counter Value Count = 0 Count = HClkTotal Count = HClkTotal - 1 Count = HClkTotal - 2 CPLoadVidClks ActiveVidClks LoadCPVidClks FrameHoldVidClks LoadHighVidClks One SPCLK per Horizontal Pixel Figure 16.
AN269 Since the remaining region widths are determined by their respective timing parameters, here are some equations to determine the number of VIDCLK periods required for the display: LoadHighVidClks = (tHSYNCH / VidClkPeriod) + 1 FrameHoldVidClks = (tHVCSYNC / VidClkPeriod) + 1 LoadCPVidClks = [(tHSYNCSPCLK - tHVCSYNC) / VidClkPeriod] + 1 CPLoadVidClks = (tSPCLKHSYNC / VidClkPeriod) + 1 Note that 1 is added to the result to round up, and tHSYNCH, tHVCSYNC, etc. are in units of seconds.
AN269 6.2.3 Vertical Alignment Signals The vertical timing alignment signals are easily determined by looking at Figure 17. Single Video Frame tVCSYNC VCSYNC HSYNC SPCLK Vertical Line Counter Value Count =0 Count = VLinesTotal Count = VLinesTotal Count = VLinesTotal - 1 Count = VLinesTotal - 2 First Line Figure 17.
AN269 Another result of having no “blank” lines is that the active region covers all of the horizontal lines, so the active region is the entire vertical width: VActiveStart = VLinesTotal VActiveStop = VLinesTotal + 1 VActiveStop is set this way to insure that pixel data is not stopped due to vertical position.
AN269 A timing diagram for this type of display is shown in Figure 18. Signal and timing names are those of the corresponding EP93xx pins. A description of the timing requirements is given in Table 7. Timing Parameter Description tHSYNCH HSYNC High pulse duration tVCHHSYNC Time from VCSYNC High to HSYNC low tSPCLKHSYNC Time from last SPCLK to HSYNC High on next line tHSYNCSPCLK Time from HSYNC Low to first SPCLK tVCLHSYNC Time from VCSYNC Low to HSync Rising Edge Table 7.
AN269 Single Horizontal Line tSPCLKHSYNC tHSYNCH tVCHHSYNC tVCLHSYNC HSYNC tHSYNCSPCLK SPCLK DATA tHVCSYNC VCSYNC (Horizontal Line 1 ONLY) One SPCLK per Horizontal Pixel Single Video Frame tVCSYNC VCSYNC HSYNC SPCLK First Line Figure 18.
AN269 6.3.1 VIDCLK and Pixel Data Clock Rate For a frame type 2 data display, the SPCLK will be gated such that clock pulses only occur during valid data, one pulse per data set. Note that the number of pixels per SPCLK may be 1, 2, 2-2/3, 4, or 8. Also, the number of VIDCLK periods per SPCLK may not always be constant. For example, in 2-2/3 mode, there are 3, 2, and then 3 VIDCLKs per SPCLK (thus an average of (3+2+3 VIDCLKs/SPCLK) with (2-2/3 pixels/SPCLK) = 1 VIDCLK/pixel).
AN269 6.3.
AN269 Single Horizontal Line tSPCLKHSYNC tHSYNCH tVCHHSYNC tVCLHSYNC HSYNC tHSYNCSPCLK SPCLK DATA tHVCSYNC VCSYNC (Horizontal Line 1 ONLY) HSyncStart HActiveStart HActiveStop Horizontal Line Counter Value Count = 0 HSyncStop HSyncStop Count = HClkTotal Count = 0 Count = HClkTotal Count = HClkTotal - 1 One SPCLK per Horizontal Pixel Figure 19. Horizontal Line for Frame Type 2 Displays Now, the number of VIDCLK periods required for the active region (i.e.
AN269 that the timing is met by making the quantity larger than it needs to be. The time from the last SPCLK until the VCSYNC signal becomes inactive (on the second line) is CPLoadVidClks. .
AN269 Since the remaining region widths are determined by their respective timing parameters, here are some equations to determine the number of VIDCLK periods required for the display: LoadHighVidClks = (tVCLHSYNC / VidClkPeriod) + 1 FrameHoldVidClks = [(tVCHHSYNC - tVCLHSYNC) / VidClkPeriod] + 1 LoadCPVidClks = (tHSYNCSPCLK / VidClkPeriod) + 1 CPLoadVidClks = [(tSPCLKHSYNC - tVCLHSYNC) / VidClkPeriod] + 1 Note that 1 is added to the result to round up.
AN269 6.3.3 Vertical Alignment Signals The vertical timing alignment signals are easily determined by looking at Figure 21. Single Video Frame tVCSYNC VCSYNC HSYNC SPCLK Vertical Line Counter Value Count =0 Count = VLinesTotal Count = VLinesTotal - 1 Count = VLinesTotal - 2 Count = VLinesTotal Count = VLinesTotal - 1 First Line Figure 21.
AN269 Note that VActiveStop is set such that data will never be stopped due to vertical position. Also, the SPCLK should not be stopped due to vertical position: VClkStart = VLinesTotal VClkStop = VLinesTotal + 1 The blank signal is not used, but it may be desired to initialize the Vertical Blanking timing registers to a known value: VBlankStart = 0 VBlankStop = 0 6.4 Other Types of Framed Data Displays The diagrams and techniques from Section 6.2 and 6.
AN269 7. GRAYSCALE LOOK-UP TABLES Each of the Red, Green, and Blue outputs from either the color look-up table (LUT) or data directly from memory can be used as indices into the Grayscale LUT. The purpose of the Grayscale LUTs is to provide a means to dither the output to low-color and monochrome displays based on X- or Y-coordinate (spatial) or frame number (temporal). In all, 8 shades (2 of which are always full off and full on) are available for each pixel’s Red, Green, and Blue components.
AN269 * * Global Data: * |>I | O | IO<|, |>dataname<| * ** END_FUNC ******************************************************************/ { INT32 x; unsigned int *GSLUTTable; switch (iLUT) { case 0: { GSLUTTable = (unsigned int *)0x80030080; break; } case 1: { GSLUTTable = (unsigned int *)0x80030280; break; } default: { GSLUTTable = (unsigned int *)0x80030300; break; } } for(x = 0;x < 32;x++) { GSLUTTable[x] = data[x]; } } const long int four_bpp_lut_gs[] = { 0x00000000, // Black 0x00202020, // 25% Gray 0x006
AN269 int start_position) /* Description: * This allows a small range of LUT entries to be replaced. * * * Exception Handling (if any): * none * * Garbage Collection (if any): * none * * Global Data: * |>I | O | IO<|, |>dataname<| * ** END_FUNC ******************************************************************/ { INT32 x; for(x = 0;x < number_of_entries;x++) { Raster->COLOR_LUT[start_position + x].
AN269 Here is the Red grayscale LUT, in the order as would be seen in the EP93xx User’s Guide table “Grayscale Look-Up Table (GrySclLUT)”. Note that the upper-order bits D[18:16] are set in all registers, but only the settings in base+0x0 through base+0x1C are used by the grayscale generator to determine if 3- or 4-count entries are used.
AN269 As mentioned in the EP93xx User’s Guide, each pixel from the frame buffer may go through the color LUT, followed by the grayscale LUT, as shown in Figure 22 (diagram shows pixel path when color and grayscale LUTs are both enabled). Gray ScaleGenerator Red[7:5] Red Grayscale LUT Green[7:5] Green Grayscale LUT 1 Blue[7:5] Blue Grayscale LUT 1 3 Pixel data from pixel MUX and blink logic Color LUT 256x24 SRAM 3 1 3 To Color Mux and Pixel Shifting Logic Figure 22.
AN269 Frame 0 HCNT =00b HCNT =01b HCNT =10b HCNT =11b HCNT =00b HCNT =01b HCNT =10b HCNT =11b VCNT=00b 0 1 0 0 0 0 0 1 VCNT=01b 0 0 1 0 1 0 0 0 VCNT=10b 0 0 0 1 0 1 0 0 VCNT=11b 1 0 0 0 0 0 1 0 Frame 2 HCNT =00b HCNT =01b HCNT =10b HCNT =11b HCNT =00b HCNT =01b HCNT =10b HCNT =11b VCNT=00b 0 0 1 0 1 0 0 0 VCNT=01b 0 1 0 0 0 0 0 1 VCNT=10b 1 0 0 0 0 0 1 0 VCNT=11b 0 0 0 1 0 1 0 0 Frame 1 Frame 3 Table 8.
AN269 For the case of Red[7:5] = 011b, the following output patterns will be generated: Frame 0 HCNT =00b HCNT =01b HCNT =10b HCNT =11b VCNT=00b 1 1 0 VCNT=01b 1 0 VCNT=10b 0 VCNT=11b HCNT =00b HCNT =01b HCNT =10b HCNT =11b 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 0 1 Frame 2 HCNT =00b HCNT =01b HCNT =10b HCNT =11b HCNT =00b HCNT =01b HCNT =10b HCNT =11b VCNT=00b 1 0 1 0 0 1 0 1 VCNT=01b 1 1 0 0 0 0 1 1 VCNT=10b 1 0 1 0 0 1
AN269 To edit the entries in the grayscale LUT, the first step is to create the pixel pattern for each frame. As noted in the EP93xx User’s Guide, there can be 3 or 4 horizontal pixels, 3 or 4 vertical pixels, and 3 or 4 video frames in the pattern.
AN269 Table entries that are don’t cares (indicated by gray shading) are written as 0, but can be written as 1.
AN269 8. RASTER MEMORY BUS BANDWIDTH CALCULATION Since the raster engine uses the main memory of the EP93xx, the total memory bandwidth should be considered when choosing a display size and bit depth for the frame buffer. Many other blocks also use the memory bus for transfers, including the USB Host port, the IDE controller, graphics accelerator, and various peripherals via the DMA engine. Note that the priorities each device is given determine the overall memory bandwidth priorities.
AN269 Appendix A: Example HSYNC/VSYNC-Style LCD Display - LG/Philips’s LB064V02-B1 The display used in this example is an LG/Philips LB064V02-B1.
AN269 values of 2, 2.5, and 3. This yields possible values of VDIV. Using those values as PDIV and VDIV, we can compute the error in VIDCLK by subtracting the desired value of SPCLK (25.2 MHz). Assuming an external clock rate of 14.745600 MHz, PLL1 = 400 MHz, PLL2 = 384 MHz, we come up with the following table of values: VDIV = fIN / (PDIV*SPCLK) Actual SPCLK Rate = fIN / (PDIV*VDIV) PDIV = 2 0 N/A[foot] PDIV = 2.5 0 N/A[foot] PDIV = 3 0 N/A[foot] PDIV = 2 8 25.0 MHz 0.2 MHz PDIV = 2.
AN269 HActiveStop = HBlankStop HActiveStop = 22 Since no clock gating is required, the HClkStart should be set to HClkTotal and HClkStop should be set to HClkStop to HClkTotal + 1 HClkStart = HClkTotal HClkStart = 799 HClkStart = HClkTotal + 1 HClkStop = 800 Now, the vertical timing register settings can be determined.
AN269 The output mode for this display (taken from table “Output Pixel Transfer Modes“ in the Raster section of the EP93xx User’s Guide) is “single pixel per clock up to 24 bits wide“ which yields the connections shown in Table 16 (level buffering may be required to meet the electrical characteristics).
AN269 Appendix B:Example Frame Type 1 Display - Kyocera’s KCS057QV1AJ-G20 For this section, we will be using the Kyocera KCS057QV1AJ-G20 3-color STN display. The relevant timing specifications from the datasheet are shown in Table 17. Timing Parameter Kyocera Datasheet Symbol Value tHSYNCH tWLPH 50 ns tHSYNCL tWLPL 370 ns tHSYNCSPCLK tLC 120-tWLPH (min 70 ns) tSPCLKHSYNC tCL 0 tHVCSYNC tFS 100 ns tVCHSYNC tFH 30 ns tSPCLK Table 17.
AN269 Once the VIDCLKDIV register has been setup, the actual VIDCLK rate can be used for setting up the horizontal LOAD/HSYNC pulse timing. To do this, we first determine the time spent on a single line.
AN269 The output mode for this display is 2-2/3 mode, and can be seen in Figures 5, 6, and 7, which yields the connections shown in Table 18 (level buffering may be required to meet the electrical characteristics).
AN269 Appendix C:Example 4-BIT STN-Style LCD Display The display used in this example is monochrome STN LCD display as HOSIDEN HLAM6323. The Relevant timing specifications taken from the datasheet are as follows: Figure 23.
AN269 The first step in setting up the EP93XX raster engine for this display involves determining the proper SPCLK rate. Using the following equations: tHORIZ = tHACTIVE + tHFRONTPORCH + tHSYNC + tHBACKPORCH tHORIZ = 80 + 2 + 1 + 7 = 90 (SPCLK periods) tVERT = tVACTIVE + tVFRONTPORCH + tVSYNC + tVBACKPORCH tVERT = 240 + 0 + 0 + 0 = 240 fVSYNC = 70 Hz SPCLK = tHORIZ * tVERT * fVSYNC SPCLK = 90 * 240 * 70 = 1512000 SPCLK periods per second (1.
AN269 Next, the Horizontal Synchronization Signals can be determined, using the following equations: HClkTotal = tHORIZ - 1 HClkTotal = 90 - 1 = 89 (SPCLK periods) Therefore: HSyncStart = HClkTotal HSyncStart = 89 HSyncStop = HClkTotal - tHSYNC HSyncStop = 89 - 1 = 88 HBlankStart = HClkTotal - tHSYNC - tHFRONTPORCH - 1= 89 - 1 - 2 - 1 = 85 HBlankStop = HClkTotal - tHSYNC - tHFRONTPORCH - tActive - 1 = 89 - 1 - 2 - 80 - 1= 5 HActiveStart = HBlankStart = 85 HActiveStop = HBlankStop = 5 HClkStart = HClkTot
AN269 Figure 24. HOSIDEN HLAM6323 Signal Timing in an EP93xx System (PIXMODE = 0x1401 - 4 Bits per Pixel) EP93XX Pin Name EP93xx Raster Signal Name STN LCD Pin Name Pin Number VCSYN HSYN PCLK P[1] P[2] P[3] P[4] BLANK P[17] Frame signal Line signal CLK B0 B1 B2 B3 YD LP XCL D0 D1 D2 D3 /DOFF M 1 11 10 6 5 4 3 13 7 AC HLM6323 Table 20.
AN269 C.1 Frame Buffer Organization, 1 Bit per Pixel, 320 x 240 32 bit Bit31 Pixel24 Byte3 … Bit24 Pixel 31 ... … Word0 Bit7 Pixel0 Byte0 … Bit0 Pixel7 … Word9 Line 0 Screen Line 239 Figure 25.
CON14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND GND 5V STN 4bit B/W LCD VEE(-20V) GND R1 CONTRAST 5V_CL1 5V_CL2 5V_FRAME 5V_DOFF 5V_D0 5V_D1 5V_D2 5V_D3 5V_M Some LCDs do not need this signal .
AN269 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied).
