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AN232

AK5393 to CS5361/81 Conversion

by Kevin L Tretter

1. Introduction

The CS5361 and CS5381 are complete analog-to-digital converters for digital audio systems. They per-

form sampling, analog-to-digital conversion and anti-alias filtering, generating 24-bit values for both left

and right channels.

The CS5361 and CS5381 offer some unique advantages over the AK5393 including:

- Over 70% REDUCTION in package size (TSSOP)

- 50% less power consumption

- 192kHz sampling capability

- Overflow detect

- Integrated level shifters

- Over 65% less group delay (48kHz output sample rate)

- External components consume less board space (See Section 2)

Table 1 shows a comparison of the key specifications of these three devices.

Table 1. Comparison of Key Specifications

AK5393 CS5361 CS5381

Conversion (Bits) 24 24 24

Dynamic Range (A-weighted) dB 117 114 120

THD+N dB -105 -105 -110

Analog Core Power Supply (VA) V +5.0 V +5.0 V +5.0 V

Digital Core Power Supply (VD) +3.3 V to +5.0 V +3.3 V to +5.0 V +3.3 V to +5.0 V

Digital Interface Power Supply (VL) N/A +2.5 V to +5.0 V +2.5 V to +5.0 V

Maximum Power mW 680 161 348

Maximum Sample Rate kHz 108 200 200

Package

28-pin SOP 24-pin SOIC/TSSOP 24-pin SOIC/TSSOP

JUL ‘03

AN232REV1

Summary of content (7 pages)

PAGE 1
AN232 AK5393 to CS5361/81 Conversion by Kevin L Tretter 1. Introduction The CS5361 and CS5381 are complete analog-to-digital converters for digital audio systems. They perform sampling, analog-to-digital conversion and anti-alias filtering, generating 24-bit values for both left and right channels.
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AN232 2. Typical Connection Diagrams +5 V to 3.3 V +5V + 1 µF 0.01 µF 0.01 µF * + 1 µF +5V to 2.5V 1 µF 0.01 µF 5.1 Ω 0.01 µF + VD VA VL FILT+ + 47 µF VL 0.01 µF REFGND 1 µF + 10 kΩ 0.
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AN232 +5V + 10µF 0.1µF 0.1µF 10 µF +5V to 3.3V 10µF VD VA VREFL + + 0.1 µF GNDL 0.22 µF ZCAL RST CAL VCOML AINL+ Analog Input Buffer (Section 8) AK5393 A/D CONVERTER HPFE SMODE2 SMODE1 DFS Reset and Calibration Control Mode Control AINLSDATA AINR+ Analog Input Buffer (Section 8) Audio Data Processor LRCK SCLK MCLK Timing Logic and Clock FSYNC AINR- VREFR 10 µF + 0.1µF GNDR 0.22 µF VCOMR AGND BGND TEST DGND Figure 3.
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AN232 3. Pin Compatibility Table 2 shows the pins of the AK5393 and the corresponding pins of the CS5361/81. Please note that the AK5393 has 28 pins, and the CS5361/81 has 24 pins.
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AN232 A system calibration can then be performed by first running the CS5361 or CS5381 with the high pass filter enabled (HPF = LOW) until the filter settles. At this point, disable the high pass filter (HPF = HI), thereby freezing the stored DC offset. 4.2 AK5393 The AK5393 will automatically initiate a calibration sequence following a reset. The CAL pin (pin 9) is an output that indicates when a calibration sequence is in progress.
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AN232 634 Ω 470 pF C0G CS5361/81 91 Ω - 1 µF AIN+ + 634 Ω 634 Ω 100 kΩ VA 2700 pF C0G 470 pF C0G 100 kΩ 3.3 kΩ 91 Ω - AIN- + 3.3 kΩ 0.01 µF 100 µF 1 µF 0.01 µF VQ 634 Ω 470 pF C0G 91 Ω - 1 µF + AIN+ 634 Ω 634 Ω 100 kΩ VA 2700 pF C0G 470 pF C0G 100 kΩ 3.3 kΩ 91 Ω - AIN- + 0.01 µF 3.3 kΩ 100 µF Figure 4. Single-Ended to Differential Input Buffer 8.2 Fully Differential Input Buffer Figure 5 shows a fully differential analog input buffer.
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AN232 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com/ IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied).