Technical information

Easy Automotive Modules
Evaluation Kit EASYKIT AUX DRIVES (FS50R07W1E3_B11A)
CAN Messages
Application Note 61 AN2012-10
Evaluation Kit EASYKIT AUX DRIVES (FS50R07W1E3_B11A)
Direction
Msg.-
name,
ID,
DLC
Update
cycle
Bit -
offset |
length
Signal name Categorie Format
Possible
range refer
to unit
[Min|Max]
Description Reaction
0|1 VRef
Ref_1V95 < 1.85 V
or Ref_1V95 > 2.05 V
1|1 TPcb T_PCB > 105 °C
2|1 TNtc T_NTC > 120 °C
3|1 IU
4|1 IV
5|1 IW
6|1 VDclMax V_DCL > 420 V
7|1 VDclMin V_DCL < 25 V wait for DCL voltage
8|1 ProgFlt
wait count overflow due to not responding
ADC routine
normal operation
is locked
9|1 WdReset last reset due to watchdog only CAN information
10|6
16|1 ULsFlt
HW trip due to phase U
low side switch test pulse
17|1 ULsVce
VU_IGBT > 7 V during phase U
low side switch test pulse
18|1 ULsI
IU_IGBT < -5 A or IU_IGBT > 5 A during phase
U low side switch test pulse
19|1 ULsVDcl
delta V_DCL before pulse and V_DCL during
phase U low side pulse > 10 V
20|1 VLsFlt
HW trip due to phase V
low side switch test pulse
21|1 VLsVce
VV_IGBT > 7 V during phase V
low side switch test pulse
22|1 VLsI
IV_IGBT < -5 A or IV_IGBT > + 5 A during
phase V low side switch test pulse
23|1 VLsVDcl
delta V_DCL before pulse and V_DCL during
phase V low side pulse > 10 V
24|1 WLsFlt
HW trip due to phase W
low side switch test pulse
25|1 WLsVce
VW_IGBT > 7 V during phase W
low side switch test pulse
26|1 WLsI
IW_IGBT < -5 A or IW_IGBT > 5 A during
phase W low side switch test pulse
27|1 WLsVDcl
delta V_DCL before pulse and V_DCL during
phase W low side pulse > 10 V
28|1 LsProgFlt
wait count overflow due to not responding
PWM or ADC routine
29|3
32|1 UHsFlt
HW trip due to phase U low and high side
switch test pulse pattern
33|1 UHsVce
(V_DCL - VU_IGBT) > (7 V + 5% of V_DCL)
during phase U high side switch pulse
34|1 UHsI
IU_IGBT < -5 A or IU_IGBT > 5 A during phase
U high side switch test pulse
35|1 UHsVDcl
delta V_DCL before pulse pattern and
V_DCL during phase U high side pulse > 10 V
36|1 VHsFlt
HW trip due to phase V low and high side
switch test pulse pattern
37|1 VHsVce
(V_DCL - VV_IGBT) > (7 V + 5% of V_DCL)
during phase V high side switch pulse
38|1 VHsI
IV_IGBT < -5 A or IV_IGBT > 5 A during phase
V high side switch test pulse
39|1 VHsVDcl
delta V_DCL before pulse pattern and
V_DCL during phase V high side pulse > 10 V
40|1 WHsFlt
HW trip due to phase V low and high side
switch test pulse pattern
41|1 WHsVce
(V_DCL - VW_IGBT) > (7 V + 5% of V_DCL)
during phase W high side switch pulse
42|1 WHsI
IW_IGBT < -5 A or IW_IGBT > 5 A during
phase W high side switch test pulse
43|1 WHsVDcl
delta V_DCL before pulse pattern and
V_DCL during phase W high side pulse > 10
44|1 HsProgFlt
wait count overflow due to not responding
PWM or ADC routine
not used
self test
active
high side
bit
[0|1]
normal operation
is locked
I_x mean value > 5 % measurement range
not used
self test
active
low side
bit
[0|1]
normal operation
is locked
Slow-
Binary,
021h,
8
write
cycle 100
ms
self test
passive
bit
[0|1]
normal operation is
locked
FsEasyKit
2Can