Specifications

Cinterion
®
PLSx3 Hardware Interface Description
2.1 Application Interface
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t PLSx3_HID_v01.003 2021-03-12
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2.1.8.1 Pulse Code Modulation Interface
PLSx3’s PCM interface can be used to connect audio devices capable of pulse code
modulation. The PCM functionality is limited to the use of wideband codec with 16kHz sample
rate only. The PCM interface runs at 16 kHz sample rate (62.5μs frame length), while the
signal processing maintains this rate in a wideband AMR call or samples automatically down
to 8kHz in a narrowband call. Therefore, the PCM sample rate is independent of the audio
bandwidth of the call.
The PCM interface has the following characteristics:
• Master mode
• Long frame synchronization
• 16kHz/8kHz sample rate
• 256, 512, 1024 and 4096kHz bit clock at 16kHz sample rate
• 256, 512, and 2048kHz bit clock at 8kHz sample rate
Table 7 lists the available PCM interface signals.
Note: PCM data is always formatted as 16-bit uncompressed two’s complement. Also, all
PCM data and frame synchronization signals are written to the PCM bus on the rising clock
edge and read on the falling edge.
2.1.8.2 Inter-IC Sound Interface
The I
2
S Interface is a standardized bidirectio zonal I
2
S based digital audio interface for trans-
mission of mono voice signals for telephony services.
The I
2
S properties and capabilities comply with the requirements lay out in the Phillips I
2
S
Bus Specifications, revised June 5, 1996.
The I
2
S interface has the following characteristics:
• Bit clock mode: Master
• Sampling rate: 8kHz (narrowband), 16kHz (wideband)
• 256kHz bit clock at 8kHz sample rate
• 512kHz bit clock at 16kHz sample rate
Table 8 lists the available I
2
S interface signals
Table 7: Overview of PCM pin functions
Signal name Signal direction
master
Description
DOUT O PCM Data from PLSx3 to external codec.
DIN I PCM Data from external codec to PLSx3.
FSC O Frame synchronization signal to external codec.
BCLK O Bit clock to external codec. Note: If the BCLK signal is
permanently
provided (AT^SAIC parameter <clk_mode> = 0), the
module will no
longer enter its power save (SLEEP) state.
MCLK - Audio master clock. Be synchronous to BCLK to use in
external codec. Can be switched on and off.