Specifications

Cinterion
®
PLSx3 Hardware Interface Description
Figures
t PLSx3_HID_v01.002d 2021-08-24
Public / Released
Page 7 of 129
Figures
Figure 1: PLSx3 system overview................................................................................. 16
Figure 2: PLSx3 block diagram ..................................................................................... 17
Figure 3: PLSx3 bottom view: Pad assignments........................................................... 20
Figure 3: PLSx3 top view: Pad assignments................................................................. 21
Figure 4: USB circuit ..................................................................................................... 28
Figure 5: Serial interface ASC0..................................................................................... 30
Figure 6: ASC0 startup behavior................................................................................... 31
Figure 7: Serial interface ASC1..................................................................................... 32
Figure 8: ASC1 startup behavior................................................................................... 33
Figure 9: Module’s two UICC/SIM/USIM interfaces ...................................................... 35
Figure 10: UICC/SIM/USIM interfaces connected........................................................... 35
Figure 11: SIM interface - enhanced ESD protection...................................................... 36
Figure 12: External UICC/SIM/USIM switch.................................................................... 37
Figure 13: Sample circuit for SIM interface connection via SIM switch........................... 37
Figure 14: GPIO startup behavior ................................................................................... 39
Figure 15: PCM timing short frame ................................................................................. 41
Figure 16: Status signaling with LED driver .................................................................... 42
Figure 17: Power indication signal .................................................................................. 43
Figure 18: Fast shutdown timing ..................................................................................... 44
Figure 19: Antenna pads (bottom view) .......................................................................... 56
Figure 20: Embedded stripline arrangement example .................................................... 57
Figure 21: Micro-Stripline arrangement example ............................................................ 58
Figure 22: Routing to application‘s RF connector ........................................................... 59
Figure 23: Routing Detail................................................................................................. 60
Figure 24: Supply voltage for active GNSS antenna....................................................... 62
Figure 25: ESD protection for passive GNSS antenna ................................................... 63
Figure 26: Schematic diagram of PLSx3 sample application.......................................... 66
Figure 27: IGT timing....................................................................................................... 68
Figure 28: Power saving and paging in GSM networks .................................................. 75
Figure 29: Power saving and paging in WCDMA networks............................................. 75
Figure 30: Power saving and paging in LTE networks.................................................... 76
Figure 31: Wake-up via RTS0......................................................................................... 77
Figure 32: Decoupling capacitor(s) for BATT+................................................................ 78
Figure 33: Power supply limits during transmit burst....................................................... 87
Figure 34: PLSx3– top and bottom view ......................................................................... 90
Figure 35: Dimensions of PLSx3 (all dimensions in mm)................................................ 91
Figure 36: Dimensions of PLSx3 (keepout area recommended) .................................... 92
Figure 37: Land pattern (top view) .................................................................................. 93
Figure 38: Recommended design for 110 micron thick stencil (top view)....................... 94
Figure 39: Recommended design for 150 micron thick stencil (top view)....................... 94
Figure 40: Reflow Profile ................................................................................................ 96
Figure 41: Carrier tape .................................................................................................. 100
Figure 42: Reel direction ............................................................................................... 100
Figure 43: Barcode label on tape reel ........................................................................... 101
Figure 44: Barcode label on tape reel - layout .............................................................. 101
Figure 45: Moisture barrier bag (MBB) with imprint....................................................... 102
Figure 46: Moisture Sensitivity Label ............................................................................ 103
Figure 47: Humidity Indicator Card - HIC ...................................................................... 104
Figure 48: Sample of VP box label................................................................................ 105
Figure 49: Reference equipment for Type Approval ..................................................... 112