Specifications

CINTERION
®
BGS12 Hardware Interface Description
Contents
7 of 109 Page
BGS12 HID_V00.
915
Confidential / Released
2019
-
01
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07
Figures
Figure 1: BGS12 system overview ..................................................................................... 21
Figure 2: BGS12 block diagram ......................................................................................... 22
Figure 3: Power supply limits during transmit burst ............................................................ 25
Figure 4: Position of reference points BATT+ and GND ..................................................... 26
Figure 5: ON circuit sample ................................................................................................ 27
Figure 6: ON timing ............................................................................................................ 28
Figure 7: Sample circuit to suppress spikes or glitches on ON signal line .......................... 29
Figure 8: Emergency shutdown/restart timing .................................................................... 30
Figure 9: Switch off behavior .............................................................................................. 33
Figure 10: Timing of CTS signal (example for a 2.12 s paging cycle) ................................. 37
Figure 11: Beginning of power saving if CFUN=7 ............................................................... 38
Figure 12: Power Saving in OFF-state ............................................................................... 38
Figure 13: External SIM card holder circuit......................................................................... 41
Figure 14: VDIG power supply domain ............................................................................... 43
Figure 15: Serial interface ASC0 ........................................................................................ 43
Figure 16: ASC0 startup behavior ...................................................................................... 45
Figure 17: Serial interface ASC1 ........................................................................................ 46
Figure 18: ASC1 startup behavior ...................................................................................... 47
Figure 19: Serial interface ASC2 ........................................................................................ 47
Figure 20: ASC1 startup behavior ...................................................................................... 48
Figure 21: Single ended microphone connection ............................................................... 49
Figure 22: Differential Microphone connection ................................................................... 50
Figure 23: Line Input .......................................................................................................... 50
Figure 24: Differential loudspeaker connection .................................................................. 51
Figure 25: Line output connection ...................................................................................... 51
Figure 26: GPIO startup behavior ...................................................................................... 53
Figure 27: I2C interface connected to VCC of application .................................................. 54
Figure 28: I2C interface connected to VDIG ....................................................................... 54
Figure 29: I2C startup behavior .......................................................................................... 55
Figure 30: Additional EEPROM to enable usage of I2C interface on DSB75 ...................... 56
Figure 31: Jumper settings to enable usage of I2C interface on DSB75 ............................. 57
Figure 32: Status signalling with LED driver ....................................................................... 58
Figure 33: Incoming voice call ............................................................................................ 59
Figure 34: incoming data receive ....................................................................................... 59
Figure 35: URC transmission ............................................................................................. 59
Figure 36: Power indication circuit ..................................................................................... 60
Figure 37: Fast Shutdown timing ........................................................................................ 61
Figure 38: Antenna pads (bottom view) .............................................................................. 62
Figure 39: Embedded Stripline with 65µm prepreg (1080) and 710µm core ....................... 63
Figure 40: Micro-Stripline on 1.0mm standard FR4 2-layer PCB - example 1 ..................... 64
Figure 41: Micro-Stripline on 1.0mm Standard FR4 PCB - example 2 ................................ 65
Figure 42: Micro-Stripline on 1.5mm Standard FR4 PCB - example 1 ................................ 66
Figure 43: Micro-Stripline on 1.5mm Standard FR4 PCB - example 2 ................................ 67
Figure 44: Pouting to application‘s RF connector - top view ............................................... 68
Figure 45: Numbering plan for connecting pads (bottom view) ........................................... 71
Figure 46: Audio programming model ................................................................................ 82
Figure 47: BGS12 – top and bottom view ........................................................................... 88
Figure 48: Dimensions of BGS12 (all dimensions in mm) (to be replaced) ......................... 89
Figure 49: Land pattern (top view) (to be replaced) ............................................................ 90
Figure 50: Recommended design for 110 micron thick stencil (top view) ........................... 91