Specifications

CINTERION

BGS12 Hardware Interface Description

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BGS12 HID_V00.

915

Confidential / Released

2019

Note: Good care should be taken when creating the PCB layout of the host application: The

traces of I2CCLK and I2CDAT should be equal in length and as short as possible.

The timing of TSU:STO and SHD:STA has deviation from the I2C specification but the I2C

interface do work properly with slave devices as verified. The deviation cannot be changed due

to limitation on the chipset.

The following figure shows the startup behavior of the I2C interface.

Figure 29: I2C startup behavior

3.14.1 I2C Interface on DSB75

To evaluate the I

C interface employing the DSB75, some modifications are required on the AH6-DSB75

adapter mentioned in Section 9.1. Four components will have to be populated on the adapter: D305 (I2C

EEPROM, SOIC-8, 1V8; a suitable EEPROM type would for example be "AT24C1024BN-SH-T" from

ATMEL), C300 (decoupling capacitor, 0402 package), R301, R302 (I2C pull-up resistors, 0402

package). For details see Figure 30.