Specifications

CINTERION
®
BGS12 Hardware Interface Description
Contents
28 of 109
Page
BGS12 HID_V00.915
Confidential / Released
2019
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01
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07
BATT
+BB
BATT
+RF
VDDLP
ON
EMERG_RST
VDIG
A high impulse starts the module up
Figure 6: ON timing
If configured to a fixed bit rate (AT+IPR≠0), the module will send the URC “^SYSSTART” which
notifies the host application that the first AT command can be sent to the module. The duration
until this URC is output varies with the SIM card and may take a couple of seconds, particularly
if the request for the SIM PIN is deactivated on the SIM card.
Please note that no “^SYSSTART” URC will be generated if autobauding (AT+IPR=0) is
enabled.
To allow the application to detect the ready state of the module we recommend using hardware
flow control which can be set with AT\Q (see [1] for details). The default setting is AT\Q0 (no
flow control) which shall be altered to AT\Q3 (RTS/CTS handshake). If the application design
does not integrate RTS/CTS lines the host application shall wait at least for the “^SYSSTART”
URC. However, if the URC is not available (due to autobauding), you will simply have to wait
for a period of time (at least 2 seconds) before assuming the module to be in ready state and
before entering any data.
Please note that no data must be sent over the ASC0 interface before the interface is active
and ready to receive data.
3.3.1.2
Suppressing Unintentional Pulses on ON Signal Line
Since the ON signal is edge triggered and a high pulse on the signal line suffices to almost im-
mediately switch on the module, it might be necessary to implement a circuit on the external
application that prevents possible spikes or glitches on the signal line from unintentionally
switching on the module. Figure 7 shows an example for such a circuit.